Datasheet

 2013 Microchip Technology Inc. DS22331A-page 97
MCP19111
15.3.1.4 PIR2 Register
The PIR2 register contains the Peripheral Interrupt
Flag bits, as shown in Register 15-5.
Note 1: Interrupt flag bits are set when an
interrupt condition occurs, regardless of
the state of its corresponding enable bit
or the Global Enable bit, GIE of the
INTCON register. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
REGISTER 15-5: PIR2 – PERIPHERAL INTERRUPT FLAG REGISTER 2
R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0
UVIF —OCIFOVIF— —VINIF—
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UVIF: Output undervoltage error interrupt flag bit
1 = Output undervoltage error has occurred
0 = Output undervoltage error has not occurred
bit 6 UNIMPLEMENTED: Read as '0'
bit 5 OCIF: Output overcurrent error interrupt flag bit
1 = Output overcurrent error has occurred
0 = Output overcurrent error has not occurred
bit 4 OVIF: Output overvoltage error interrupt flag bit
1 = Output overvoltage error has occurred
0 = Output overvoltage error has not occurred
bit 3-2 UNIMPLEMENTED: Read as '0'
bit 1 VINIF: V
IN
Status bit
1 = V
IN
is below acceptable level
0 = V
IN
is at acceptable level
bit 0 UNIMPLEMENTED: Read as '0'
TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 93
OPTION_REG
RAPU INTEDG T0CE T0SE PSA PS2 PS1 PS0 75
PIE1 — ADIE BCLIE SSPIE — — TMR2IE TMR1IE 94
PIE2 UVIE
—OCIEOVIE— — VINIE — 95
PIR1
— ADIF BCLIF SSPIF — — TMR2IF TMR1IF 96
PIR2 UVIF
—OCIFOVIF— — VINIF — 97
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.