Datasheet

 2013 Microchip Technology Inc. DS22331A-page 95
MCP19111
15.3.1.2 PIE2 Register
The PIE2 register contains the Peripheral Interrupt
Enable bits, as shown in Register 15-3.
Note 1: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 15-3: PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0
UVIE —OCIEOVIE— — VINIE —
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UVIE: Output Under Voltage Interrupt enable bit
1 = Enables the UV interrupt
0 = Disables the UV interrupt
bit 6 UNIMPLEMENTED: Read as '0'
bit 5 OCIE: Output Overcurrent Interrupt enable bit
1 = Enables the OC interrupt
0 = Disables the OC interrupt
bit 4 OVIE: Output Overvoltage Interrupt enable bit
1 = Enables the OV interrupt
0 = Disables the OV interrupt
bit 3-2 UNIMPLEMENTED: Read as '0'
bit 1 VINIE: V
IN
UVLO Interrupt Enable
1 = Enables the V
IN
UVLO interrupt
0 = Disables the V
IN
UVLO interrupt
bit 0 UNIMPLEMENTED: Read as '0'