Datasheet

MCP19111
DS22331A-page 94  2013 Microchip Technology Inc.
15.3.1.1 PIE1 Register
The PIE1 register contains the Peripheral Interrupt
Enable bits, as shown in Register 15-2.
Note 1: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 15-2: PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
— ADIE BCLIE SSPIE — — TMR2IE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UNIMPLEMENTED: Read as '0'
bit 6-0 ADIE: ADC Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 6-0 BCLIE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP Bus Collision Interrupt
0 = Disables the MSSP Bus Collision Interrupt
bit 6-0 SSPIE: Synchronous Serial Port (MSSP) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 6-0 UNIMPLEMENTED: Read as 0
bit 6-0 TMR2IE: Timer2 Interrupt Enable
1 = Enables the Timer2 interrupt
0 = Disables the Timer2 interrupt
bit 6-0 TMR1IE: Timer1 Interrupt Enable
1 = Enables the Timer1 interrupt
0 = Disables the Timer1 interrupt