Datasheet

 2013 Microchip Technology Inc. DS22331A-page 93
MCP19111
15.3 Interrupt Control Registers
15.3.1 INTCON REGISTER
The INTCON register is a readable and writable regis-
ter, that contains the various enable and flag bits for the
TMR0 register overflow, interrupt-on-change and exter-
nal INT pin interrupts.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 15-1: INTCON – INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE IOCE T0IF INTF IOCF
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3 IOCE: Interrupt-on-Change Enable bit
(1)
1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
(2)
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: External Interrupt Flag bit
1 = The external interrupt occurred (must be cleared in software)
0 = The external interrupt did not occur
bit 0 IOCF: Interrupt-on-Change Interrupt Flag bit
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state
Note 1: IOC register must also be enabled.
2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clear-
ing T0IF bit.