Datasheet

 2013 Microchip Technology Inc. DS22331A-page 89
MCP19111
14.7 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Table 14- 4 and Table 14-5 show the Reset
conditions of these registers.
PMDATH 195h --00 0000 --00 0000 --uu uuuu
OSCCAL 198h -xxx xxxx -uuu uuuu -uuu uuuu
DOVCAL 199h ---- xxxx ---- uuuu ---- uuuu
TTACAL 19Ah ---- xxxx ---- uuuu ---- uuuu
BGRCAL 19Bh ---- xxxx ---- uuuu ---- uuuu
VROCAL 19Ch ---- xxxx ---- uuuu ---- uuuu
ZROCAL 19Dh ---- xxxx ---- uuuu ---- uuuu
ATSTCON 19F 1--- 0001 1--- 0001 u--- uuuu
TABLE 14-3: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Register Address
Power-on
Reset
MCLR
Reset
WDT Reset
Wake-up from Sleep through
Interrupt
Wake-up from Sleep through
WDT Time-out (Continued)
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If V
DD
goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIRx will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 14-5 for Reset value for specific condition.
TABLE 14-4: RESET STATUS BITS AND
THEIR SIGNIFICANCE
POR TO PD Condition
011Power-on Reset
u0uWDT Reset
u00WDT Wake-up from Sleep
u10Interrupt Wake-up from Sleep
uuuMCLR
Reset during normal
operation
u10MCLR Reset during Sleep
00xNot allowed. TO
is set on POR
0x0Not allowed. PD
is set on POR
TABLE 14-5: RESET CONDITION FOR SPECIAL REGISTERS (Note 2)
Condition
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset 0000h 0001 1xxx ---- -u0-
MCLR Reset during normal operation 0000h 000u uuuu ---- -uu-
MCLR
Reset during Sleep 0000h 0001 0uuu ---- -uu-
WDT Reset 0000h 0000 uuuu ---- -uu-
WDT Wake-up from Sleep PC + 1 uuu0 0uuu ---- -uu-
Interrupt Wake-up from Sleep PC + 1
(1)
uuu1 0uuu ---- -uu-
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack
and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.