Datasheet

 2013 Microchip Technology Inc. DS22331A-page 85
MCP19111
14.3 Power-up Timer (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR Reset. The
Power-up Timer operates from an internal RC
oscillator. The chip is kept in Reset as long as PWRT is
active. The PWRT delay allows the V
DD
to rise to an
acceptable level. A Configuration bit (P
WRTE), can
disable (if set) or enable (if cleared or programmed) the
Power-up Timer.
The Power-up Timer delay will vary from chip-to-chip
due to:
•V
DD
variation
• Temperature variation
• Process variation
14.4 Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 17.0
“Watchdog Timer (WDT)” for more information.
14.5 Power-Up Timer
The Power-up Timer optionally delays device execution
after a POR event. This timer is typically used to allow
V
DD
to stabilize before allowing the device to start
running.
The Power-up Timer is controlled by the PWRTE bit of
Configuration Word.
14.6 Start-up Sequence
Upon the release of a POR, the following must occur
before the device will begin executing:
• Power-up Timer runs to completion (if enabled)
• Oscillator start-up timer runs to completion
•MCLR
must be released (if enabled)
The total time-out will vary based on PWRTE
bit status.
For example, with PWRTE
bit erased (PWRT disabled),
there will be no time-out at all. Figures 14-3, 14-4
and 14-5 depict time-out sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR
high will begin execution immediately
(see Figure 14-4). This is useful for testing purposes or
to synchronize more than one MCP19111 device
operating in parallel.
14.6.1 POWER CONTROL (PCON)
REGISTER
The Power Control register PCON (address 8Eh) has
two Status bits to indicate what type of Reset occurred
last.
FIGURE 14-3: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
Note: Voltage spikes below V
SS
at the MCLR
pin, inducing currents greater than 80 mA,
may cause latch-up. Thus, a series resis-
tor of 50-100 should be used when
applying a “low” level to the MCLR
pin,
rather than pulling this pin directly to V
SS
.
T
PWRT
T
IOSCST
V
DD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset