Datasheet

MCP19111
DS22331A-page 84  2013 Microchip Technology Inc.
14.1 Power-on Reset (POR)
The on-chip POR circuit holds the chip in Reset until
V
DD
has reached a high enough level for proper
operation. To take advantage of the POR, simply
connect the MCLR
pin through a resistor to V
DD
. This
will eliminate external RC components usually needed
to create Power-on Reset.
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure proper operation. If these conditions are not
met, the device must be held in Reset until the
operating conditions are met.
14.2 MCLR
MCP19111 has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR
pin low.
Voltages applied to the MCLR
pin that exceed its
specification can result in both MCLR
Resets and
excessive current beyond the device specification
during the ESD event. For this reason, Microchip
recommends that the MCLR
pin no longer be tied
directly to V
DD
. The use of an RC network, as shown in
Figure 14-2, is suggested.
An internal MCLR
option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the MCLR
pin
becomes an external Reset input. In this mode, the
MCLR pin has a weak pull-up to V
DD
.
FIGURE 14-2: RECOMMENDED MCLR
CIRCUIT
TABLE 14-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR TO PD Condition
011Power-on Reset
u0uWDT Reset
u00WDT Wake-up
uuuMCLR
Reset during normal operation
u10MCLR
Reset during Sleep
Legend: u = unchanged, x = unknown
Note: The POR circuit does not produce an
internal Reset when V
DD
declines. To
re-enable the POR, V
DD
must reach V
SS
for a minimum of 100 µs.
V
DD
MCLR
R
1
1k (or greater)
C
1
0.1 µF
(optional, not critical)
R2
100 
(needed with
SW1
(optional)
MCP19111
capacitor)