Datasheet

 2013 Microchip Technology Inc. DS22331A-page 55

MCP19111

8.0 SYSTEM BENCH TESTING

To allow for easier system design and bench testing,

the MCP19111 device features a multiplexer used to

output various internal analog signals. These signals

can be measured on the GPA0 pin through a unity gain

buffer. The configuration control of the GPA0 pin is

found in the ATSTCON register, as shown in

Control of the signals present at the output of the unity

gain buffer is found in the BUFFCON register, as shown

in Register 8-2.

8.1 Analog Bench Test Control

8.1.1 ATSTCON REGISTER

The ATSTCON register contains the bits used to dis-

able the MOSFET drivers and configure the GPA0 pin

as the unity gain buffer out, as shown in Register 8-1.

Note 1: The DRVDIS bit is reset to ‘1’ so the high-

side and low-side drivers are in a known

state after reset. This bit must be cleared

by software for normal operation.

R/W-1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1

Reserved — — Reserved HIDIS LODIS BNCHEN DRVDIS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Reserved

bit 6-5 Unimplemented: Read as ‘0’

bit 4 Reserved

bit 3 HIDIS: High-side driver control bit

1 = High-side driver is disabled

0 = High-side driver is enabled

bit 2 LODIS: Low-side driver control bit

1 = Low-side driver is disabled

0 = low-side driver is enabled

bit 1 BNCHEN: GPA0 bench test configuration control bit

1 = GPA0 is configured for analog bench test output

0 = GPA0 is configured for normal operation

bit 0 DRVDIS: MOSFET driver disable control bit

1 = High-side and low-side drivers are set low, PHASE pin is floating

0 = High-side and low-side drivers are set for normal operation