Datasheet

 2013 Microchip Technology Inc. DS22331A-page 3
MCP19111
TABLE 1: 28-PIN SUMMARY
I/O
28-Pin QFN
ANSEL
A/D
Timers
MSSP
Interrupt
Pull-up
Basic Additional
GPA0 1 Y AN0 — — IOC Y — Analog Debug Output
(1)
GPA1 2 Y AN1 — — IOC Y — Sync Signal In/Out
(2, 3)
GPA2 3 Y AN2 T0CKI — IOC
INT
Y — —
GPA3 5 Y AN3 — IOC Y — —
GPA4 9 N — — — IOC N — —
GPA5 8 N — — — IOC
(4)
Y
(5)
MCLR —
GPA6 7 N — — — IOC N —
GPA7 6 N — — SCL IOC N —
GPB0 10 N — — SDA IOC N — —
GPB1 26 Y AN4 — — IOC Y — Error Signal In/Out
(3)
GPB2 28 Y AN5 — — IOC Y — —
GPB4 4 Y AN6 — — IOC Y ICSPDAT
ICDDAT
—
GPB5 27 Y AN7 — — IOC Y ICSPCLK
ICDCLK
Alternate Sync
Signal In/Out
(2, 3)
GPB6 21 N — — — IOC Y — —
GPB7 11 N — — — IOC Y — —
V
IN
13 N — — — — — V
IN
Device Input Voltage
V
DR
16 N — — — — — V
DR
Gate Drive Supply Input
Voltage
V
DD
20 N — — — — — V
DD
Internal Regulator Output
GND 12 N — — — — — GND Small Signal Ground
P
GND
14 N — — — — — — Large Signal Ground
LDRV 15 N — — — — — — Low-Side MOSFET
Connection
HDRV 18 N — — — — — — High-Side MOSFET
Connection
PHASE 17 N — — — — — — Switch Node
BOOT 19 N — — — — — — Floating Bootstrap Supply
+V
SEN
24 N — — — — — — Output Voltage
Differential Sense
-V
SEN
25 N — — — — — — Output Voltage
Differential Sense
+I
SEN
23 N — — — — — — Current Sense Input
-I
SEN
22 N — — — — — — Current Sense Input
Note 1: The Analog Debug Output is selected when the ATSTCON<BNCHEN> bit is set.
2: Selected when device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0> bits
in the BUFFCON register.
3: Selected when device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bits in
the BUFFCON register.
4: The IOC is disabled when MCLR
is enabled.
5: Weak pull-up always enabled when MCLR
is enabled, otherwise the pull-up is under user control.