Datasheet

MCP19111
DS22331A-page 20  2013 Microchip Technology Inc.
3.10.3 OUTPUT POWER GOOD
The output voltage measured between the +V
SEN
and
-V
SEN
pins can be monitored by the internal ADC. In
firmware, when this ADC reading matches a user
defined power good value, a GPIO can be toggled to
indicate the system output voltage is within a specified
range. Delays, hysteresis and time out values can all
be configured in firmware.
3.10.4 OUTPUT VOLTAGE SOFT-START
During start-up, soft start of the output voltage is
accomplished in firmware. By using one of the internal
timers and incrementing the OVCCON or OVFCON
register on a timer overflow, very long soft start times
can be achieved.
3.10.5 OUTPUT VOLTAGE TRACKING
The MCP19111 can be configured to track another
voltage signal at start-up or shutdown. The ADC is
configured to read a GPIO that has the desired tracking
voltage applied to it. The firmware then handles the
tracking of the internal output voltage reference to this
ADC reading.
3.10.6 MULTI-PHASE SYSTEM
In a multi-phase system the output of each converter is
connected together. There is one master device that
sets the system switching frequency and provides each
slave device with an error signal, in order to regulate
the output to the same value.
The MCP19111 can be configured as a multi-phase
master or slave by the setting of the MLTPH<2:0> bits
in the BUFFCON register (Register 8-2). When set as
a multi-phase master device, the internal switching fre-
quency clock is connected to GPA1 and the output of
the error amplifier is connected to GPB1. The GPIOs
need to be configured as outputs.
When set as a multi-phase slave device, the GPA1 pin
is configured as the CLKPIN function. The switching
frequency clock from the master device must be
connected to GPA1. The slave device will synchronize
its internal switching frequency clock to the master
clock. Phase shift can be applied by setting the
PWMPHL register of the slave device. The slave GPB1
pin is configured as the error signal input pin (EAPIN).
The master error amplifier output must be connected to
GPB1. Gain can be added to the master error amplifier
output signal by the SLVGNCON register setting
(Register 6-8). The slave device will use this master
error signal to regulate the output voltage. When set as
a slave device, GPA1 and GPB1 need to be configured
as inputs. Refer to Section 26.1 “Standard Pulse-
Width Modulation (PWM) Mode” for additional
information
.
3.10.7 MULTIPLE OUTPUT SYSTEM
In a multiple output system, the switching frequency of
each converter should be synchronized to a master
clock to prevent beat frequencies from developing.
Phase shift is often added to the master clock to help
smooth the system input current. The MCP19111 has
the ability to function as a multiple output master or
slave by setting the appropriate MLTPH<2:0> bits in
the BUFFCON register (Register 8-2).
When configured as a multiple output master, the
GPA1 pin is set as the CLKPIN output function. The
internal switching frequency clock is applied to this pin
and is to be connected to the GPA1 pin of the slave
units.
When configured as a multiple output slave, the GPA1
pin is set as the CLKPIN input function. The switching
frequency clock of the master device is connected to
this pin. Phase shift can be applied by appropriately
setting the PWMPHL register of the slave device. Refer
to Section 26.1 “Standard Pulse-Width Modulation
(PWM) Mode”.
3.10.8 SYSTEM BENCH TESTING
The MCP19111 is a highly integrated controller. To
facilitate system prototyping, various internal signals
can be measured by configuring the MCP19111 in
bench test mode. To accomplish this, the
ATSTCON<BNCHEN> bit is set. This configures GPA0
as the ANALOG_TEST feature. The signals measured
on GPA0 are controlled by the ASEL<4:0> bits of the
BUFFCON register. See Section 8.0 “System Bench
Testing” for more information.
Note 1: The ALT_CLKPIN can also be used by
setting the APFCON<CLKSEL> bit.
Note 1: The ALT_CLKPIN can also be used by
setting the APFCON<CLKSEL> bit.
Note 1: The factory-set calibration words are
write protected even when the
MCP19111 is placed in a Bench Test
mode.