Datasheet

 2013 Microchip Technology Inc. DS22331A-page 185
MCP19111
REGISTER 27-5: SSPCON3: SSP CONTROL REGISTER 3
R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ACKTIM: Acknowledge Time Status bit (I
2
C mode only)
(2)
1 = Indicates the I
2
C bus is in an Acknowledge sequence, set on the 8
th
falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on the 9
th
rising edge of SCL clock
bit 6 PCIE: Stop Condition Interrupt Enable bit (I
2
C mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
(1)
bit 5 SCIE: Start Condition Interrupt Enable bit (I
2
C mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
(1)
bit 4 BOEN: Buffer Overwrite Enable bit
In I
2
C Master mode:
This bit is ignored.
In I
2
C Slave mode:
1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state
of the SSPOV bit only if the BF bit = 0.
0 = SSPBUF is only updated when SSPOV is clear
bit 3 SDAHT: SDA Hold Time Selection bit
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I
2
C Slave mode only)
If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF
bit of the PIR2 register is set, and bus goes Idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1 AHEN: Address Hold Enable bit (I
2
C Slave mode only)
1 = Following the 8
th
falling edge of SCL for a matching received address byte; CKP bit of the
SSPCON1 register will be cleared and the SCL will be held low.
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I
2
C Slave mode only)
1 = Following the 8
th
falling edge of SCL for a received data byte; slave hardware clears the CKP bit
of the SSPCON1 register and SCL is held low.
0 = Data holding is disabled
Note 1: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
2: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.