Datasheet
2013 Microchip Technology Inc. DS22331A-page 183
MCP19111
REGISTER 27-3: SSPCON1: SSP CONTROL REGISTER 1
R/C/HS-0 R/C/HS-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSPBUF register was attempted while the I
2
C conditions were not valid for a
transmission to be started
0 = No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
(1)
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t
care” in Transmit mode (must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
(2)
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In I
2
C Slave mode:
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I
2
C Master mode:
Unused in this mode
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = Reserved
0001 = Reserved
0010 = Reserved
0011 = Reserved
0100 = Reserved
0101 = Reserved
0110 = I
2
C Slave mode, 7-bit address
0111 = I
2
C Slave mode, 10-bit address
1000 = I
2
C Master mode, clock = F
OSC
/(4 x (SSPADD+1))
(3)
1001 = Reserved
1010 = Reserved
1011 = I
2
C firmware controlled Master mode (Slave idle)
1100 = Reserved
1101 = Reserved
1110 = I
2
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I
2
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, the SDA and SCL pins must be configured as inputs.
3: SSPADD values of 0, 1 or 2 are not supported for I
2
C Mode.