Datasheet

 2013 Microchip Technology Inc. DS22331A-page 181
MCP19111
27.6 BAUD RATE GENERATOR
The MSSP module has a Baud Rate Generator
available for clock generation in I
2
C Master mode. The
Baud Rate Generator (BRG) reload value is placed in
the SSPADD register (Register 27-7). When a write
occurs to SSPBUF, the Baud Rate Generator will
automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in Figure 27-32 triggers the
value from SSPADD to be loaded into the BRG counter.
This occurs twice for each oscillation of the module
clock line. The logic dictating when the reload signal is
asserted depends on the mode the MSSP is being
operated in.
Table 27-2 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 27-1:
FIGURE 27-32: BAUD RATE GENERATOR BLOCK DIAGRAM
F
CLOCK
F
OSC
SSPADD 1+4
----------------------------------------------=
SSPM<3:0>
BRG Down Counter
SSPCLK
F
OSC
/2
SSPADD<7:0>
SSPM<3:0>
SCL
Reload
Control
Reload
Note: Values of 0x00, 0x01 and 0x02 are not valid
for SSPADD when used as a Baud Rate
Generator for I
2
C. This is an implementation
limitation.
TABLE 27-2: MSSP CLOCK RATE W/BRG
F
OSC
F
CY
BRG Value
F
CLOCK
(2 Rollovers of BRG)
8 MHz 2 MHz 04h 400 kHz
(1)
8 MHz 2 MHz 0Bh 166 kHz
8 MHz 2 MHz 13h 100 kHz
Note 1: The I
2
C interface does not conform to the 400 kHz I
2
C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.