Datasheet

MCP19111
DS22331A-page 168  2013 Microchip Technology Inc.
FIGURE 27-17: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
27.5.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set, it indicates that an action on SSPBUF
was attempted while the module was not Idle.
27.5.4 I
2
C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN bit of the SSPCON2 register. If the
SDA and SCL pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPADD<7:0> and starts its count. If SCL and SDA
are both sampled high when the Baud Rate Generator
times out (T
BRG
), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPSTAT1
register to be set. Following this, the Baud Rate
Generator is reloaded with the contents of
SSPADD<7:0> and resumes its count. When the Baud
Rate Generator times out (T
BRG
), the SEN bit of the
SSPCON2 register will be automatically cleared by
hardware; the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
FIGURE 27-18: FIRST START BIT TIMING
SDA
SCL
SCL deasserted but slave holds
DX ‚ – 1DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
Note 1: If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is
aborted and the I
2
C module is reset into
its Idle state.
2: The Philips I
2
C Specification states that a
bus collision cannot occur on a Start.
SDA
SCL
S
T
BRG
1
st
bit
2
nd
bit
T
BRG
SDA = 1,
At completion of Start bit,
SCL = 1
Write to SSPBUF occurs here
T
BRG
hardware clears SEN bit
T
BRG
Write to SEN bit occurs here
Set S bit (SSPSTAT<3>)
and sets SSPIF bit