Datasheet

 2013 Microchip Technology Inc. DS22331A-page 151
MCP19111
27.4 I
2
C SLAVE MODE OPERATION
The MSSP Slave mode operates in one of the four
modes selected in the SSPM bits of SSPCON1
register. The modes can be divided into 7-bit and
10-bit Addressing mode. 10-bit Addressing mode
operate the same as 7-bit, with some additional
overhead for handling the larger addresses.
Modes with Start and Stop bit interrupts operate the
same as the other modes. The exception is the SSPIF
bit getting set upon detection of a Start, Restart or Stop
condition.
27.4.1 SLAVE MODE ADDRESSES,
SSPADD
The SSPADD register (Register 27-7) contains the
Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPBUF register and an
interrupt is generated. If the value does not match, the
module goes idle and no indication is given to the
software that anything happened.
The SSPMSK register (Register 27-6) affects the
address matching process. See Section 27.4.10
“SSPMSKx Register” for more information.
27.4.2 SECOND SLAVE MODE ADDRESS,
SSPADD2
The SSPADD2 register (Register 27-9) contains a
second Slave mode address. To enable the use of this
second Slave mode address, bit 0 must be set. The
first byte received after a Start or Restart condition is
compared against the value stored in this register. If
the byte matches, the value is loaded into the
SSPBUF register and an interrupt is generated. If the
value does not match, the module goes Idle and no
indication is given to the software that anything
happened.
The SSPMSK2 register, Register 27-8, affects the
address matching process. See Section 27.4.10
“SSPMSKx Register” for more information.
27.4.2.1 I
2
C Slave 7-bit Addressing Mode
In 7-bit Addressing mode, the LSb of the received data
byte is ignored when determining if there is an address
match.
27.4.2.2 I
2
C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb of the 10-bit address and
stored in bits 2 and 1 of the SSPADDx register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPADDx
with the low address. The low address byte is clocked
in and all 8 bits are compared to the low address value
in SSPADDx. Even if there is not an address match;
SSPIF and UA are set, and SCL is held low until
SSPADDx is updated to receive a high byte again.
When SSPADDx is updated, the UA bit is cleared. This
ensures the module is ready to receive the high
address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing
communication. A transmission can be initiated by
issuing a Restart once the slave is addressed, and
clocking in the high address with the R/W
bit set. The
slave hardware will then acknowledge the read
request and prepare to clock out data. This is only
valid for a slave after it has received a complete high
and low address byte match.
27.4.3 SLAVE RECEPTION
When the R/W bit of a matching received address byte
is clear, the R/W
bit of the SSPSTAT register is cleared.
The received address is loaded into the SSPBUF
register and acknowledged.
When an overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF of the SSPSTAT
register is set, or bit SSPOV of the SSPCON1 register
is set. The BOEN bit of the SSPCON3 register modifies
this operation. For more information, see
Register 27-5.
An MSSP interrupt is generated for each transferred
data byte. Flag bit, SSPIF, must be cleared by software.
When the SEN bit of the SSPCON2 register is set, SCL
will be held low (clock stretch) following each received
byte. The clock must be released by setting the CKP
bit of the SSPCON1 register, except sometimes in
10-bit mode.