Datasheet

 2013 Microchip Technology Inc. DS22331A-page 149
MCP19111
27.3.4 SDA HOLD TIME
The hold time of the SDA pin is selected by the SDAHT
bit of the SSPCON3 register. Hold time is the time SDA
is held valid after the falling edge of SCL. Setting the
SDAHT bit selects a longer 300 ns minimum hold time
and may help on buses with large capacitance.
27.3.5 START CONDITION
The I
2
C specification defines a Start condition as a
transition of SDA from a high to a low state, while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state. Figure 27-4 shows the wave
forms for Start and Stop conditions.
A bus collision can occur on a Start condition if the
module samples the SDA line low before asserting it
low. This does not conform to the I
2
C Specification,
that states no bus collision can occur on a Start.
27.3.6 STOP CONDITION
A Stop condition is a transition of the SDA line from
low-to-high state while the SCL line is high.
27.3.7 RESTART CONDITION
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
In 10-bit Addressing Slave mode, a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, match-
ing both high and low address bytes, the master can
issue a Restart and the high address byte with the
R/W
bit set. The slave logic will then hold the clock
and prepare to clock out data.
After a full match with R/W
clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop
condition, a high address with R/W
clear or a high
address match fails.
TABLE 27-1: I
2
C BUS TERMS
TERM Description
Transmitter The device which shifts data out onto the bus.
Receiver The device which shifts data in from the bus.
Master The device that initiates a transfer, generates clock signals and terminates a transfer.
Slave The device addressed by the master.
Multi-Master A bus with more than one device that can initiate data transfers.
Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration
ensures that the message is not corrupted.
Synchronization Procedure to synchronize the clocks of two or more devices on the bus.
Idle No master is controlling the bus, and both SDA and SCL lines are high.
Active Any time one or more master devices are controlling the bus.
Addressed Slave Slave device that has received a matching address and is actively being clocked by a master.
Matching Address Address byte that is clocked into a slave that matches the value stored in SSPADDx.
Write Request Slave receives a matching address with R/W
bit clear, and is ready to clock in data.
Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of
the Slave. This data is the next and all following bytes until a Restart or Stop.
Clock Stretching When a device on the bus hold SCL low to stall communication.
Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high
state.
Note: At least one SCL low time must appear
before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.