Datasheet

MCP19111
DS22331A-page 146  2013 Microchip Technology Inc.
FIGURE 27-2: MSSP BLOCK DIAGRAM (I
2
C SLAVE MODE)
27.2 I
2
C MODE OVERVIEW
The Inter-Integrated Circuit Bus (I
2
C) is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment, where the master
devices initiate the communication. A Slave device is
controlled through addressing.
The MSSP module has eight registers for I
2
C
operation. They are the:
• MSSP Status Register (SSPSTAT)
• MSSP Control Register1 (SSPCON1)
• MSSP Control Register2 (SSPCON2)
• MSSP Control Register3 (SPPCON3)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) - Not directly
accessible
• MSSP Address Register (SSPADD)
• MSSP Address Register2 (SSPADD2)
• MSSP Address Mask Register1 (SSPMSK)
• MSSP Address Mask Register2 (SSPMSK2)
The SSPCON1 register is used to define the I
2
C mode.
Four selection bits (SSPCON1<3:0>) allow one of the
following I
2
C modes to be selected:
•I
2
C Slave mode (7-bit address)
•I
2
C Slave mode (10-bit address)
•I
2
C Master mode, clock = OSC/4 (SSPADD +1)
•I
2
C firmware controlled Master mode (Slave idle)
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the data received byte
was data or address, if the next byte is completion of
the 10-bit address, and if this will be a read or write data
transfer.
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operation, the
SSPBUF and SSPSR create a double buffer receiver.
This allows reception of the next byte to begin before
reading the last byte of received data. When the
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and the
SSPOV bit (SSPCON1<6>) is set and the byte in the
SSPSR is lost.
Read Write
SSPSR Reg
Match Detect
SSPADD Reg
Start and
Stop bit Detect
SSPBUF Reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT Reg)
SCL
SDA
Shift
Clock
MSb
LSb
SSPMSK Reg