Datasheet

MCP19111
DS22331A-page 138  2013 Microchip Technology Inc.
25.0 TIMER2 MODULE
The Timer2 module is an 8-bit timer with the following
features:
• 8-bit timer register (TMR2)
• 8-bit period register (PR2)
• Interrupt on TMR2 match with PR2
• Software programmable prescaler (1:1, 1:4, 1:16)
See Figure 25-1 for a block diagram of Timer2.
25.1 Timer2 Operation
The clock input to the Timer2 module is the system
clock (F
OSC
). The clock is fed into the Timer2 prescaler,
which has prescale options of 1:1, 1:4 or 1:16. The
output of the prescaler is then used to increment the
TMR2 register.
The values of TMR2 and PR2 are constantly compared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, TMR2 is reset to 00h on the next
increment cycle.
The match output of the Timer2/PR2 comparator is
used to set the TMR2IF interrupt flag bit in the PIR1
register.
The TMR2 and PR2 registers are both fully readable
and writable. On any Reset, the TMR2 register is set to
00h and the PR2 register is set to FFh.
Timer2 is turned on by setting the TMR2ON bit in the
T2CON register to a ‘1’. Timer2 is turned off by clearing
the TMR2ON bit to a ‘0’.
The Timer2 prescaler is controlled by the T2CKPS bits
in the T2CON register. The prescaler counter are
cleared when:
• A write to TMR2 occurs.
• A write to T2CON occurs.
• Any device Reset occurs (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset).
FIGURE 25-1: TIMER2 BLOCK DIAGRAM
Note: TMR2 is not cleared when T2CON is
written.
Comparator
TMR2
Sets Flag
TMR2
Output
Reset
Prescaler
PR2
2
F
OSC
1:1, 1:4, 1:8, 1:16
EQ
bit TMR2IF
T2CKPS<1:0>