Datasheet

 2013 Microchip Technology Inc. DS22331A-page 13
MCP19111
2.1.10 GPB1 PIN
GPB1 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.
AN4 is an input to the A/D. To configure this pin to be
read by the A/D on channel 4, bits TRISB1 and ANSB1
must be set.
When the MCP19111 is configured as a multiple output
or multi-phase MASTER or SLAVE, this pin is config-
ured to be the error amplifier signal input or output. See
Section 3.10.6 “Multi-Phase System” and
Section 3.10.7 “Multiple Output System”, for more
information.
2.1.11 GPB2 PIN
GPB2 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.
AN5 is an input to the A/D. To configure this pin to be
read by the A/D on channel 5, bits TRISB2 and ANSB2
must be set.
2.1.12 GPB4 PIN
GPB4 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.
AN6 is an input to the A/D. To configure this pin to be
read by the A/D on channel 6, bits TRISB4 and ANSB4
must be set.
ISCPDAT is the primary serial programming data input
function. This is used in conjunction with ICSPCLK to
serial program the device.
2.1.13 GBP5 PIN
GPB5 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.
AN7 is an input to the A/D. To configure this pin to be
read by the A/D on channel 7, bits TRISB5 and ANSB5
must be set.
ISCPCLK is the primary serial programming clock func-
tion. This is used in conjunction with ICSPDAT to serial
program the device.
This pin can also be configured as an alternate switch-
ing frequency synchronization input or output,
ALT_CLKPIN, for use in multiple output or multi-phase
systems. See Section 19.1 “Alternate Pin Function”
for more information.
2.1.14 GPB6 PIN
GPB6 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.
2.1.15 GPB7 PIN
GPB7 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.
2.1.16 V
IN
PIN
Device input power connection pin. It is recommended
that capacitance be placed between this pin and the
GND pin of the device.
2.1.17 V
DD
PIN
The output of the internal +5.0V regulator is connected
to this pin. It is recommended that a 1.0 µF bypass
capacitor be connected between this pin and the GND
pin of the device. The bypass capacitor should be
placed physically close to the device.
2.1.18 V
DR
PIN
The 5V supply for the low-side driver is connected to
this pin. The pin can be connected by an RC filter to the
V
DD
pin.
2.1.19 GND PIN
GND is the small signal ground connection pin. This pin
should be connected to the exposed pad, on the
bottom of the package.
2.1.20 P
GND
PIN
Connect all large signal level ground returns to P
GND
.
These large-signal level ground traces should have a
small loop area and minimal length to prevent coupling
of switching noise to sensitive traces.
2.1.21 LDRV PIN
The gate of the low-side or rectifying MOSFET is
connected to LDRV. The PCB tracing connecting LDRV
to the gate must be of minimal length and appropriate
width to handle the high peak drive currents and fast
voltage transitions.
2.1.22 HDRV PIN
The gate of the high-side MOSFET is connected to
HDRV. This is a floating driver referenced to PHASE.
The PCB trace connecting HDRV to the gate must be
of minimal length and appropriate width to handle the
high peak drive current and fast voltage transitions.