Datasheet

 2013 Microchip Technology Inc. DS22331A-page 129
MCP19111
22.4 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
HOLD
) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 22-4. The source
impedance (R
S
) and the internal sampling switch (R
SS
)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (R
SS
)
impedance varies over the device voltage (V
DD
), refer
to Figure 22-4.
The maximum recommended impedance for
analog sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 22-1 may be used. This equation
assumes that 1/2 LSb error is used (1,024 steps for the
ADC). The 1/2 LSb error is the maximum error allowed
for the ADC to meet its specified resolution.
EQUATION 22-1: ACQUISITION TIME EXAMPLE
Note 1: The charge holding capacitor (C
HOLD
) is not discharged after each conversion.
2: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
T
ACQ
Amplifier Settling Time Hold Capacitor Charging Time Temperature Coefficient++=
T
AMP
T
C
T
COFF
++=
2 µs T
C
Temperature - 25°C0.05 µs/°C++=
T
C
C
HOLD
R
IC
R
SS
R
S
++ ln(1/2047)–=
10 pF 1 k  7 k  10 k  ++– ln(0.0004885)=
1.37=µs
V
APPLIED
1e
T
C
–
RC
----------
–





V
APPLIED
1
1
2
n1+
1–
------------------------------–



=
V
APPLIED
1
1
2
n1+
1–
------------------------------–



V
CHOLD
=
V
APPLIED
1e
T
C
–
RC
----------
–





V
CHOLD
=
;[1] V
CHOLD
charged to within 1/2 lsb
;[2] V
CHOLD
charge response to V
APPLIED
;combining [1] and [2]
The value for T
C
can be approximated with the following equations:
Solving for T
C
:
Therefore:
Temperature +50°C and external impedance of 10 k
 5.0V V
DD
=
Assumptions:
Note: Where n = number of bits of the ADC.
T
ACQ
2 µs 1.37µs 50°C- 25°C0.05µs/°C++=
4.67 µs=