Datasheet

MCP19111
DS22331A-page 12  2013 Microchip Technology Inc.
2.1 Detailed Pin Functional
Description
2.1.1 GPA0 PIN
GPA0 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPA. An
internal weak pull-up and interrupt-on-change are also
available.
AN0 is an input to the A/D. To configure this pin to be
read by the A/D on channel 0, bits TRISA0 and ANSA0
must be set.
When the ATSTCON<BNCHEN> bit is set, this pin is
configured as the ANALOG_TEST function. It is a
buffered output of the internal analog signal
multiplexer. Signals present on this pin are controlled
by the BUFFCON register, see Register 8-2.
2.1.2 GPA1 PIN
GPA1 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPA. An
internal weak pull-up and interrupt-on-change are also
available.
AN1 is an input to the A/D. To configure this pin to be
read by the A/D on channel 1, bits TRISA1 and ANSA1
must be set.
When the MCP19111 is configured as a multiple output
or multi-phase MASTER or SLAVE, this pin is
configured to be the switching frequency
synchronization input or output, CLKPIN. See
Section 3.10.6 “Multi-Phase System” and
Section 3.10.7 “Multiple Output System” for more
information.
2.1.3 GPA2 PIN
GPA2 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPA. An
internal weak pull-up and interrupt-on-change are also
available.
AN2 is an input to the A/D. To configure this pin to be
read by the A/D on channel 2, bits TRISA2 and ANSA2
must be set.
When bit T0CS is set, the T0CKI function is enabled.
See Section 23.0 “Timer0 Module” for more
information.
GPA2 can also be configured as an external interrupt
by setting of the INTE bit. See Section 15.2 “GPA2/
INT Interrupt” for more information.
2.1.4 GPA3 PIN
GPA3 is a general purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPA. An
internal weak pull-up and interrupt-on-change are also
available.
AN3 is an input to the A/D. To configure this pin to be
read by the A/D on channel 3, bits TRISA3 and ANSA3
must be set.
2.1.5 GPA4 PIN
GPA4 is a true open drain general purpose pin whose
data direction is controlled in TRISGPA. There is no
internal connection between this pin and device V
DD
,
making this pin ideal to be used as an SMBus Alert pin.
This pin does not have a weak pull-up, but interrupt-on-
change is available.
2.1.6 GPA5 PIN
GPA5 is a general purpose TTL input-only pin. An inter-
nal weak pull-up and interrupt-on-change are also
available.
For programming purposes, this pin is to be connected
to the MCLR
pin of the serial programmer. See
Section 28.0 “In-Circuit Serial Programming™
(ICSP™)” for more information.
2.1.7 GPA6 PIN
GPA6 is a general purpose CMOS input/output pin
whose data direction is controlled in TRISGPA. An
interrupt-on-change is also available.
2.1.8 GPA7 PIN
GPA7 is a true open drain general purpose pin whose
data direction is controlled in TRISGPA. There is no
internal connection between this pin and device V
DD
.
This pin does not have a weak pull-up, but interrupt-on-
change is available.
When the MCP19111 is configured for I
2
C
communication (see Section 27.2 “I
2
C Mode
Overview”), GPA7 functions as the I
2
C clock, SCL.
2.1.9 GPB0 PIN
GPB0 is a true open drain general purpose pin whose
data direction is controlled in TRISGPB. There is no
internal connection between this pin and device V
DD
.
This pin does not have a weak pull-up, but
interrupt-on-change is available.
When the MCP19111 is configured for I
2
C
communication (see Section 27.2 “I
2
C Mode
Overview”), GPB0 functions as the I
2
C clock, SDA.