Datasheet

MCP19111
DS22331A-page 110  2013 Microchip Technology Inc.
19.1 Alternate Pin Function
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 19-1. For this device family, the
following function can be moved between different
pins.:
• Frequency Synchronization Clock Input/Output
This bit has no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
19.2 PORTGPA and TRISGPA Registers
PORTGPA is an 8-bit wide, bidirectional port consisting
of five CMOS I/O, two open drain I/O, and one open
drain input-only pin. The corresponding data direction
register is TRISGPA (Register 19-3). Setting a
TRISGPA bit (= 1) will make the corresponding
PORTGPA pin an input (i.e., disable the output driver).
Clearing a TRISGPA bit (= 0) will make the
corresponding PORTGPA pin an output (i.e., enables
output driver). The exception is GPA5, which is input
only and its TRISGPA bit will always read as ‘1’.
Example 19-1 shows how to initialize an I/O port.
Reading the PORTGPA register (Register 19-2) reads
the status of the pins, whereas writing to it will write to
the PORT latch. All write operations are read-modify-
write operations.
The TRISGPA register (Register 19-3) controls the
PORTGPA pin output drivers, even when they are
being used as analog inputs. The user must ensure the
bits in the TRISGPA register are maintained set when
using them as analog inputs. I/O pins configured as
analog input always read ‘0’. If the pin is configured for
a digital output (either port or alternate function), the
TRISGPA bit must be cleared in order for the pin to
drive the signal, and a read will reflect the state of the
pin.
19.2.1 INTERRUPT-ON-CHANGE
Each PORTGPA pin is individually configurable as an
interrupt-on-change pin. Control bits IOCB<7:4> and
IOCB<2:0> enable or disable the interrupt function for
each pin. The interrupt-on-change feature is disabled
on a Power-on Reset. Reference Section 20.0
“Interrupt-On-Change” for more information.
19.2.2 WEAK PULL-UPS
PORTGPA <3:0> and PORTGPA5 have an internal weak
pull-up. PORTGPA<7:6> are special ports for the SSP
module and do not have weak pull-ups. Individual control
bits can enable or disable the internal weak pull-ups (see
Register 19-4). The weak pull-up is automatically turned
off when the port pin is configured as an output, an
alternative function or on a Power-on Reset setting the
RAPU
bit of the OPTION register. The weak pull-up on
GPA5 is enabled when configured as MCLR
pin by setting
bit 5 of the Configuration word, and disabled when GPA5
is an I/O. There is no software control of the MCLR pull-
up.
REGISTER 19-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CLKSEL
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 Unimplemented: Read as ‘0’
bit 0 CLKSEL: Pin Selection bit
1 = Multi-phase or multiple output clock function is on GPB5
0 = Multi-phase or multiple output clock function is on GPA1