Datasheet
MCP19111
DS22331A-page 100 2013 Microchip Technology Inc.
16.1.1 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction:
- SLEEP instruction will execute as an NOP
- WDT and WDT prescaler will not be cleared
-TO
bit of the STATUS register will not be set
-PD
bit of the STATUS register will not be
cleared
• If the interrupt occurs during or after the
execution of a SLEEP instruction:
- SLEEP instruction will be completely
executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
-TO
bit of the STATUS register will be set
-PD bit of the STATUS register will be cleared
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD
bit. If the PD bit is set, the SLEEP instruction
was executed as an NOP.
FIGURE 16-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC
Interrupt flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency
(1)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h)
Inst(0005h)
Inst(0004h)
Dummy Cycle
PC + 2 0004h 0005h
Dummy Cycle
T
OST
PC + 2
Note 1: GIE = 1 assumed. In this case, after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution
will continue in-line.
TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register on
Page
INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 93
IOCA IOCA7 IOCA6 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 120
IOCB IOCB7 IOCB6 IOCB5 IOCB4
— IOCB2 IOCB1 IOCB0 120
PIE1
— ADIE BCLIE SSPIE — — TMR2IE TMR1IE 94
PIE2 UVIE —OCIEOVIE— —VINIE— 95
PIR1 — ADIF BCLIF SSPIF — — TMR2IF TMR1IF 96
PIR2 UVIF
—OCIFOVIF— — VINIF — 97
STATUS
IRP RP1 RP0 TO PD ZDCC 69
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.