MCP19111 Digitally Enhanced Power Analog Controller with Integrated Synchronous Driver Synchronous Buck Features: Microcontroller Features: • • • • • • Precision 8 MHz Internal Oscillator Block: - Factory Calibrated • Interrupt Capable - Firmware - Interrupt-on-Change Pins • Only 35 Instructions to Learn • 4096 Words On-Chip Program Memory • High Endurance Flash: - 100,000 write Flash Endurance - Flash Retention: >40 years • Watchdog Timer (WDT) with Independent Oscillator for Reliable Operation • Progra
MCP19111 GPB2 GPB5 GPB1 -VSEN +VSEN +ISEN -ISEN 28 27 26 25 24 23 22 Pin Diagram – 28-Pin QFN (MCP19111) GPA0 1 21 GPB6 GPA1 2 20 VDD GPA2 3 19 BOOT GPB4 4 18 HDRV GPA3 5 17 PHASE GPA7 6 16 VDR 15 LDRV MCP19111 EXP-29 DS22331A-page 2 8 9 10 11 12 13 14 GPA4 GPB0 GPB7 GND VIN PGND 7 GPA5/MCLR GPA6 2013 Microchip Technology Inc.
MCP19111 Timers MSSP 1 Y AN0 — — GPA1 2 Y AN1 — — GPA2 3 Y AN2 T0CKI GPA3 5 Y AN3 GPA4 9 N — — Pull-up A/D GPA0 Interrupt I/O ANSEL 28-PIN SUMMARY 28-Pin QFN TABLE 1: Basic Additional IOC Y — Analog Debug Output (1) IOC Y — Sync Signal In/Out (2, 3) — IOC INT Y — — — IOC Y — — — IOC N — — MCLR — — (4) IOC (5) GPA5 8 N — — Y GPA6 7 N — — — IOC N — GPA7 6 N — — SCL IOC N — GPB0 10 N — — SDA IOC N — — GPB1 26
MCP19111 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Pin Description ........................................................................................................................................................................... 10 3.0 Functional Description ......................................................................
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MCP19111 NOTES: DS22331A-page 6 2013 Microchip Technology Inc.
MCP19111 1.0 DEVICE OVERVIEW After initial device configuration using Microchip’s MPLAB® X Integrated Development Environment (IDE) software, the PMBus or I2C can be used by a host to communicate with, or modify, the operation of the MCP19111. The MCP19111 is a highly integrated, mixed signal, analog pulse-width modulation (PWM) current mode controller with an integrated microcontroller core for synchronous DC/DC step-down applications.
MCP19111 SYNCHRONOUS BUCK BLOCK DIAGRAM VIN Bias Gen dc current sense gain VDD VDD LDO1 To ADC LDO2 VIN VDR AVDD 3 +ISEN BGAP CSDGEN bit 5R 4 -ISEN ac current sense gain R +ISEN UVLO VDAC 6 BOOT 8 VOUT OV OV REF 5 8 VIN VOUT UV UV REF OC Comp 8+5 HDRV VREGREF PHASE BGAP AVDD 4 Lo_on -ISEN DLY 4 Slave Mode VOUT VOUT LVL_SFT LDRV +VSEN VDR -VSEN 2013 Microchip Technology Inc.
MCP19111 FIGURE 1-3: MICROCONTROLLER CORE BLOCK DIAGRAM Configuration 13 Flash 4K x 14 Program Memory Program Bus PORTA GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 RAM 256 bytes File Registers 8 Level Stack (13-bit) 14 8 Data Bus Program Counter RAM Addr GPA6 GPA7 9 Addr MUX Instruction reg Direct Addr 7 8 Indirect Addr PORTB GPB0 FSR reg GPB1 GPB2 STATUS reg 8 3 Instruction Decode & Control TESTCLKIN Timing Generation GPB4 GPB5 MUX Power-up Timer GPB6 GPB7 ALU Power-on Reset Watchdog Timer 8
MCP19111 2.0 PIN DESCRIPTION The 28-Lead MCP19111 device features pins that have multiple functions associated with each pin. Table 2-1 provides a description of the different functions. See Section 2.1 “Detailed Pin Functional Description” for more detailed information. TABLE 2-1: MCP19111 PINOUT DESCRIPTION Name GPA0/AN0/ANALOG_TEST GPA1/AN1/CLKPIN Function Input Type Output Type GPA0 TTL CMOS General purpose I/O AN0 AN — A/D Channel 0 input.
MCP19111 TABLE 2-1: MCP19111 PINOUT DESCRIPTION (CONTINUED) Name GPB5/AN7/ICSPCLK/ ALT_CLKPIN Function Input Type Output Type GPB5 TTL CMOS Description General purpose I/O AN7 AN — A/D Channel 7 input ISCPCLK ST — Primary Serial Programming Clock ALT_CLKPIN — — Alternate switching frequency clock input or output (2,3) GPB6 GPB6 TTL CMOS General purpose I/O GPB7 GPB7 TTL CMOS General purpose I/O VIN VIN — — Device input supply voltage VDD VDD — — Internal +5V LDO outp
MCP19111 2.1 2.1.1 Detailed Pin Functional Description GPA0 PIN GPA0 is a general purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPA. An internal weak pull-up and interrupt-on-change are also available. AN0 is an input to the A/D. To configure this pin to be read by the A/D on channel 0, bits TRISA0 and ANSA0 must be set. When the ATSTCON bit is set, this pin is configured as the ANALOG_TEST function.
MCP19111 2.1.10 GPB1 PIN GPB1 is a general purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPB. An internal weak pull-up and interrupt-on-change are also available. AN4 is an input to the A/D. To configure this pin to be read by the A/D on channel 4, bits TRISB1 and ANSB1 must be set. When the MCP19111 is configured as a multiple output or multi-phase MASTER or SLAVE, this pin is configured to be the error amplifier signal input or output. See Section 3.10.
MCP19111 2.1.23 PHASE PIN The PHASE pin provides the return path for the highside gate driver. The source of the high-side MOSFET, drain of the low-side MOSFET and the inductor are connected to this pin. 2.1.24 BOOT PIN The BOOT pin is the floating bootstrap supply pin for the high-side gate driver. A capacitor is connected between this pin and the PHASE pin to provide the necessary charge to turn on the high-side MOSFET. 2.1.
MCP19111 3.0 FUNCTIONAL DESCRIPTION 3.1 Linear Regulators Two internal linear regulators generate two 5V rails. One 5V rail is used to provide power for the internal analog circuitry and is contained on-chip. The second 5V rail provides power to the internal PIC core and it is present on the VDD pin. It is recommended that a 1 µF capacitor be placed between VDD and PGND. The VDR pin provides power to the internal synchronous MOSFET driver.
MCP19111 Individual control of the HDRV or LDRV signal is accomplished by setting or clearing the HIDIS or LODIS bits in the ATSTCON register. When either driver is disabled, the output signal is set low. 3.3 The MCP19111 contains a unity gain differential amplifier used for remote sensing of the output voltage. Connect the +VSEN and -VSEN pins directly at the load for better load regulation. The +VSEN and -VSEN are the positive and negative inputs, respectively, of the differential amplifier.
MCP19111 The value of RS and CS can be found by using Equation 3-3. When the current sense filter time constant is set equal to the inductor time constant, the voltage appearing across CS approximates the current flowing in the inductor, multiplied by the inductor resistance.
MCP19111 3.8 3.8.1 Protection Features INPUT UNDER VOLTAGE LOCKOUT The input under voltage lockout (UVLO) threshold is configurable by the VINLVL register, Register 6-1. When the voltage at the VIN pin of the MCP19111 is below the configurable threshold, the PIR2 flag will be set. This flag is cleared by hardware once the VIN voltage is greater than the configurable threshold.
MCP19111 3.8.5 OVERTEMPERATURE The MCP19111 features a hardware shutdown protection typically set firmware fault-handling procedure shutdown the MCP19111 for an condition. 3.9 overtemperature at +160°C. No is required to overtemperature PIC Microcontroller Core Integrated into the MCP19111 is the PIC microcontroller mid-range core. This is a fully functional microcontroller, allowing proprietary features to be implemented. Setting the CONFIG bit enables the code protection.
MCP19111 3.10.3 OUTPUT POWER GOOD The output voltage measured between the +VSEN and -VSEN pins can be monitored by the internal ADC. In firmware, when this ADC reading matches a user defined power good value, a GPIO can be toggled to indicate the system output voltage is within a specified range. Delays, hysteresis and time out values can all be configured in firmware. 3.10.4 OUTPUT VOLTAGE SOFT-START During start-up, soft start of the output voltage is accomplished in firmware.
MCP19111 4.0 ELECTRICAL CHARACTERISTICS 4.1 ABSOLUTE MAXIMUM RATINGS (†) VIN – VGND .................................................................................................................................................. -0.3V to +32V VBOOT - VIN ................................................................................................................................................. -0.3V to +6.5V VPHASE (continuous) ......................................................................
MCP19111 4.2 Electrical Characteristics Electrical Specifications: Unless otherwise noted, VIN = 12V, VREF = 1.2V, FSW = 300 kHz, TA = +25°C. Boldface specifications apply over the TA range of -40°C to +125°C. Parameter Symbol Min Typ Max Units VIN 4.5 — 32 V Conditions Input Input Voltage IQ — 5 10 mA Not switching Shutdown Current ISHDN — 1.8 2.
MCP19111 4.2 Electrical Characteristics (Continued) Electrical Specifications: Unless otherwise noted, VIN = 12V, VREF = 1.2V, FSW = 300 kHz, TA = +25°C. Boldface specifications apply over the TA range of -40°C to +125°C. Parameter Symbol Min Typ Max Units Conditions Current Sense DC Gain Offset Voltage IDC_OFFSET 1.4 1.56 1.7 V Voltage for Zero Current VZC — 1.45 — V VZCCON = 0x80h Adjustable VOUT Range VOUT_RANGE 0.5 — 3.
MCP19111 4.2 Electrical Characteristics (Continued) Electrical Specifications: Unless otherwise noted, VIN = 12V, VREF = 1.2V, FSW = 300 kHz, TA = +25°C. Boldface specifications apply over the TA range of -40°C to +125°C. Parameter Symbol Min Typ Max Units Conditions Internal Oscillator Frequency FOSC 7.60 8.00 8.40 MHz Switching Frequency FSW — FOSC/N — kHz Switching Frequency Range Select N 5 — 80 — (N–1)/N — %/ 100 DTSTEP — 4 — ns RHDRV-SCR — 1 2.
MCP19111 4.2 Electrical Characteristics (Continued) Electrical Specifications: Unless otherwise noted, VIN = 12V, VREF = 1.2V, FSW = 300 kHz, TA = +25°C. Boldface specifications apply over the TA range of -40°C to +125°C. Parameter Symbol Min Typ Max Units Conditions VDD 4.6 5.0 5.4 V VIN = 6.0V to 32V, Note 2 AVDD — 5.0 — V VIN = 6.0V to 32V, Note 2 IDD 30 — — mA Line Regulation VDD/ (VDD x VIN) — 0.05 0.1 %/V (VDD+1.0V) VIN 20V Note 2 Load Regulation VDD/VDD -1.
MCP19111 4.2 Electrical Characteristics (Continued) Electrical Specifications: Unless otherwise noted, VIN = 12V, VREF = 1.2V, FSW = 300 kHz, TA = +25°C. Boldface specifications apply over the TA range of -40°C to +125°C. Parameter Symbol Min Typ Max Units Conditions GPIO Input High Voltage VIH 2.0 — VDD V I/O Port with TTL buffer, VDD = 5V, TA = +90°C 0.8VDD — VDD V I/O Port with Schmitt Trigger buffer, VDD = 5V, TA = +90°C 0.
MCP19111 5.0 DIGITAL ELECTRICAL CHARACTERISTICS 5.1 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
MCP19111 5.2 AC Characteristics: MCP19111 (Industrial, Extended) FIGURE 5-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC 1 2 TABLE 5-1: Param No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Typ† Max Units FOSC Oscillator Frequency(1) — 8 — MHz 1 TOSC 2 TCY Oscillator Period(1) Instruction Cycle Time(1) — 250 — ns — 1000 — ns Conditions * † These parameters are characterized but not tested.
MCP19111 TABLE 5-2: Param No.
MCP19111 TABLE 5-3: Param No.
MCP19111 FIGURE 5-6: PWM TIMING PWM (CLKPIN) 53 Note: TABLE 5-5: 54 Refer to Figure 5-1 for load conditions. PWM REQUIREMENTS Param No. Sym Characteristic Min 53* TccR PWM (CLKPIN) output rise time — 10 25 ns TccF PWM (CLKPIN) output fall time — 10 25 ns 54* * † Typ† Max Units Conditions These parameters are characterized but not tested. Data in “Typ” column is at VIN = 12V (VDD = 5V), +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
MCP19111 TABLE 5-7: MCP19111 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym AD130* TAD Characteristic A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Min Typ† 1.6 — 9.0 µs TOSC-based, VREF 3.0V 3.0 — 9.0 µs TOSC-based, VREF full range 3.0 6.0 9.0 µs ADCS<1:0> = 11 (ADRC mode) At VDD = 2.5V 1.6 4.0 6.0 µs At VDD = 5.
MCP19111 FIGURE 5-8: A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO 134 131 Q4 130 A/D CLK 9 A/D DATA 8 7 6 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF GO SAMPLE DONE 132 SAMPLING STOPPED Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2013 Microchip Technology Inc.
MCP19111 NOTES: DS22331A-page 34 2013 Microchip Technology Inc.
MCP19111 6.0 CONFIGURING THE MCP19111 The MCP19111 is an analog controller with digital peripheral. This means that device configuration is handled through register settings instead of adding external components. The following sections detail how to set the analog control registers. 6.1 The VINLVL bit must be set to enable the input under voltage lockout circuitry.
MCP19111 6.2 Output Overcurrent The MCP19111 features a cycle-by-cycle peak current limit. By monitoring the OCIF interrupt flag, custom overcurrent fault handling can be implemented. To detect an output overcurrent, the MCP19111 senses the voltage drop across the high-side MOSFET while it is conducting. Leading edge blanking is incorporated to mask the overcurrent measurement for a given amount of time. This helps prevent false overcurrent readings.
MCP19111 REGISTER 6-2: OCCON: OUTPUT OVERCURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x OCEN OCLEB1 OCLEB0 OOC4 OOC3 OOC2 OOC1 OOC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OCEN: Output Overcurrent DAC Control bit 1 = Output Overcurrent DAC is enabled 0 = Output Overcurrent DAC is disabled bit 6-5 OCLEB<1:0>: Leading Edge Blanking 00 = 114 ns bl
MCP19111 6.3 Current Sense AC Gain The current measured across the inductor is a square wave that is averaged by the capacitor (CS) connected between +ISEN and -ISEN. This very small voltage plus the ripple can be amplified by the current sense AC gain circuitry. The amount of gain is controlled by the CSGSCON register.
MCP19111 6.4 Current Sense DC Gain DC gain can be added to the sensed inductor current to allow it to be read by the ADC. The amount of DC gain added is controlled by the CSDGCON register. Adding DC gain to the current sense signal used by the control loop may also be needed in some multi-phase systems to account for device and component differences. The CSDGEN bit determines if the gained current sense signal is added back to the AC current signal (see Register 6-4).
MCP19111 6.5 Voltage for Zero Current In multi-phase systems it may be necessary to provide some offset to the sensed inductor current. The VZCCON register can be used to provide a positive or negative offset in the sensed current. Typically, the VZCCON will be set to 0x80h, which corresponds to the sensed inductor current centered around 1.45V. However, by adjusting the VZCCON register, this centered voltage can be shifted up or down by approximately 3.28 mV per step.
MCP19111 6.6 FIGURE 6-1: Compensation Setting The MCP19111 uses a peak current mode control architecture. A control reference is used to regulate the peak current of the converter directly. The inner current loop essentially turns the inductor into a voltagecontrolled current source. This reduces the control-tooutput transfer function to a simple single-pole model of a current source feeding a capacitor.
MCP19111 6.7 Slope Compensation A negative voltage slope is added to the output of the error amplifier. This is done to prevent subharmonic instability when: 1. 2. The amount of negative slope added to the error amplifier output is controlled by Register 6-7. The slope compensation is enabled by setting the SLCPBY bit in the ABECON register. the operating duty cycle is greater than 50% wide changes in the duty cycle occur.
MCP19111 6.8 MASTER Error Signal Gain Note: When operating in a multi-phase system, the output of the MASTER’s error amplifier is used by all SLAVE devices as their control signal. It is important to balance the current in all phases to maintain a uniform temperature across all phases. Component tolerances make this balancing difficult. Each SLAVE device has the ability to gain or attenuate the MASTER error signal depending upon the settings of Register 6-8.
MCP19111 6.9 MOSFET Driver Programmable Dead Time FIGURE 6-2: The turn-on delay of the high-side and low-side drive signals can be configured independently to allow different MOSFETs and circuit board layouts to be used to construct an optimized system. See Figure 6-2. HDRV Setting the HDLYBY and LDLYBY bits of the PE1 register enables the high-side and low-side delay, respectively. The amount of delay added is controlled in the DEADCON register. See Register 6-9 for more information.
MCP19111 6.10 Output Voltage Configuration Note: Two registers control the error amplifier reference voltage. The reference is coarsely set in 15 mV steps and then finely adjusted in 0.82 mV steps above the coarse setting (see Registers 6-10 and 6-11). Higher output voltages can be achieved by using a voltage divider connected between the output and the +VSEN pin. Care must be taken to ensure maximum voltage rating compliance on all pins.
MCP19111 6.11 Output Under Voltage The output voltage is monitored, and when it is below the output under voltage threshold, the UVIF flag is set. This flag must be cleared in software. See Section 15.3.1.4 “PIR2 Register” for more information. The output under voltage threshold is controlled by the OUVCON register, as shown in Register 6-12.
MCP19111 6.13 Analog Peripheral Control The MCP19111 has various analog peripherals. These peripherals can be configured to allow customizable operation. Refer to Register 6-14 more information. 6.13.1 DIODE EMULATION MODE The MCP19111 can operate in either diode emulation or synchronous rectification mode. When operating in diode emulation mode, the LDRV signal is terminated when the voltage across the low-side MOSFET is approximately 0V.
MCP19111 REGISTER 6-14: PE1: ANALOG PERIPHERAL ENABLE 1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DECON DVRSTR HDLYBY LDLYBY PDEN PUEN UVTEE OVTEE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DECON: Diode Emulation Mode bit 1 = Diode emulation mode enabled 0 = Synchronous rectification mode enabled bit 6 DVRSTR: High-Side Drive Strength Configuration b
MCP19111 6.14 Analog Blocks Enable Control Various analog circuit blocks can be enabled or disabled, as shown in Register 6-15. Addition enable bits are located in the ATSTCON register. 6.14.1 OUTPUT OVERVOLTAGE ENABLE The output overvoltage is enabled by setting the ABECON bit. Clearing this bit will disable the output overvoltage circuitry and cause the setting in the OOVCON register to be ignored. 6.14.
MCP19111 REGISTER 6-15: ABECON: ANALOG BLOCK ENABLE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OVDCEN UVDCEN MEASEN SLCPBY CRTMEN TMPSEN RECIREN PATHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OVDCEN: Output over voltage DAC control bit 1 = Output over voltage DAC is enabled 0 = Output over voltage DAC is disabled bit 6 UVDCEN: Output under voltage
MCP19111 7.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
MCP19111 Note: Unless otherwise indicated, VIN = 12V, FSW = 300 kHz, TA = +25°C. 5.07 5.06 3.35 3.33 5.04 5.03 - 40ºC +25ºC VREGREF (V) VDD (V) 5.05 5.02 OVCCON = 0xDCh 3.34 +125ºC 3.32 3.31 3.30 3.29 3.28 5.01 3.27 5.00 3.26 4.99 3.25 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Current (mA) FIGURE 7-7: VDD vs. Output Current. -40 -25 -10 20 35 50 65 80 95 110 125 Temperature (ºC) FIGURE 7-10: VREGREF vs. Temperature (VREGREF = 3.3V). 80 OVCCON = 0x28h 0.62 0.61 0.60 0 59 0.
MCP19111 Note: Unless otherwise indicated, VIN = 12V, FSW = 300 kHz, TA = +25°C. 1.4 8.05 DRVSTR = 0 Oscillattor Frequency (MHz) HDR RV Resistance ( ) 1.3 1.2 1.1 1.0 RHDRV-SOURCE 0.9 0.8 0.7 0.6 RHDRV-SINK 0.5 0.4 -40 -25 -10 5 FIGURE 7-13: Temperature. CR RNT Voltage (V) HDR RV Resistance ( ) RHDRV-SOURCE 1.5 1.0 RHDRV-SINK 0.5 -40 -25 -10 5 FIGURE 7-14: Temperature. HDRV RDSon vs. RLDRV-SOURCE 1.0 0.8 0.6 RLDRV-SINK 0.2 -40 -25 -10 FIGURE 7-15: Temperature. 5 7.99 7.98 7.97 7.
MCP19111 NOTES: DS22331A-page 54 2013 Microchip Technology Inc.
MCP19111 8.0 SYSTEM BENCH TESTING 8.1 To allow for easier system design and bench testing, the MCP19111 device features a multiplexer used to output various internal analog signals. These signals can be measured on the GPA0 pin through a unity gain buffer. The configuration control of the GPA0 pin is found in the ATSTCON register, as shown in Register 8-1. Control of the signals present at the output of the unity gain buffer is found in the BUFFCON register, as shown in Register 8-2. REGISTER 8-1: 8.1.
MCP19111 8.2 Unity Gain Buffer When measuring signals with the unity gain buffer, the buffer offset must be added to the measured signal. The factory measured buffer offset can be read from memory location 2087h. Refer to Section 11.1.1 “Reading Program Memory as Data” for more information. The unity gain buffer module is used during a multiphase application and while operating in Bench Test mode.
MCP19111 9.0 DEVICE CALIBRATION 9.1 Calibration Word 1 The DOV<3:0> bits at memory location 2080h set the offset calibration for the output voltage remote sense differential amplifier. Firmware must read these values and write them to the DOVCAL register for proper calibration. Read-only memory locations 2080h through 208Fh contain factory calibration data. Refer to Section 18.0 “Flash Program Memory Control” for information on how to read from these memory locations.
MCP19111 9.2 Calibration Word 2 The TTA<3:0> bits at memory location 2082h calibrate the overtemperature shutdown threshold point. Firmware must read these values and write them to the TTACAL register for proper calibration. The BGR<3:0> bits at memory location 2082h calibrate the internal band gap. Firmware must read these values and write them to the BGRCAL register for proper calibration.
MCP19111 9.3 Calibration Word 3 The VRO<3:0> bits at memory location 2083h calibrate the offset of the buffer amplifier of the output voltage regulation reference set point. This effectively changes the band gap reference. Firmware must read these values and write them to the VROCAL register for proper calibration. The ZRO<3:0> bits at memory location 2083h calibrate the offset of the error amplifier. Firmware must read these values and write them to the ZROCAL register for proper calibration.
MCP19111 9.4 Calibration Word 4 The TANA<9:0> bits at memory location 2084h contain the ADC reading from the internal temperature sensor when the silicon temperature is at +30°C. The temperature coefficient of the internal temperature sensor is 16 mV/°C.
MCP19111 9.5 Calibration Word 5 The DIFC<7:0> bits at memory location 2085h contain the offset voltage information for the output voltage difference amplifier. The value is an 8-bit two’s complement number that represents the number of the OVCCON counts needed to adjust for the differential amplifier offset. This value can be used to completely remove the differential amplifier offset. For example, the offset of the differential amplifier is measured to be -64 mV.
MCP19111 9.6 Calibration Word 6 The DIFF<7:0> bits at memory location 2086h contain the offset voltage information for the output voltage difference amplifier. The value is an 8-bit two’s complement number that represents the number of the OVFCON counts needed to adjust for the differential amplifier offset. This value can be used to completely remove the differential amplifier offset. For example, the offset of the differential amplifier is measured to be +4.2 mV. Since one OVFCON count equals 0.
MCP19111 9.7 Calibration Word 7 The BUFF<7:0> bits at memory location 2087h represent the offset voltage of the unity gain buffer. This is an 8-bit two’s complement number. The MSB is the sign bit. If the MSB is set to 1, the resulting number is negative.
MCP19111 NOTES: DS22331A-page 64 2013 Microchip Technology Inc.
MCP19111 10.0 RELATIVE EFFICIENCY MEASUREMENT 7. With a constant input voltage, output voltage and load current, any change in the high-side MOSFET on-time represents a change in the system efficiency. The MCP19111 is capable of measuring the on-time of the high-side MOSFET. Therefore, the relative efficiency of the system can be measured and optimized by changing the system parameters, such as switching frequency, driver dead time or high-side drive strength. 10.
MCP19111 NOTES: DS22331A-page 66 2013 Microchip Technology Inc.
MCP19111 11.0 MEMORY ORGANIZATION FIGURE 11-1: PROGRAM MEMORY MAP AND STACK FOR MCP19111 There are two types of memory in the MCP19111: • Program Memory • Data Memory - Special Function Registers (SFRs) - General Purpose RAM 11.1 Program Memory Organization The MCP19111 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 4K x 14 (0000h-0FFFh) is physically implemented.
MCP19111 11.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set a Files Select Register (FSR) to point to the program memory. 11.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 11-1.
MCP19111 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. Therefore, it is recommended that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see the Section 29.
MCP19111 11.3 DATA MEMORY TABLE 11-1: MCP19111 DATA MEMORY MAP File Address File Address File Address File Address Indirect addr.(1) 00h Indirect addr. (1) 80h Indirect addr.(1) 100h Indirect addr.
MCP19111 TABLE 11-2: Adr Name MCP19111 SPECIAL REGISTERS SUMMARY BANK 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets(1) Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 02h PCL 03h STATUS 04h FSR 05h PORTGPA GPA7 GPA6 06h PORTGPB GPB7 GPB6 07h PIR1 — ADIF 08h PIR2 UVIF — 09h PCON —
MCP19111 TABLE 11-3: Addr MCP19111 SPECIAL REGISTERS SUMMARY BANK 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Values on all other resets(1) Bank 1 80h INDF 81h OPTION_REG Addressing this location uses contents of FSR to address data memory (not a physical register) 82h PCL 83h STATUS 84h FSR 85h TRISGPA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 86h TRISGPB TRISB7 TRISB6 TRISB5 TRISB4 87h PIE1 — ADIE BCLIE 88h PIE2 UVIE — 89h APFCON — —
MCP19111 TABLE 11-4: Adr Name MCP19111 SPECIAL REGISTERS SUMMARY BANK 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets(1) Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 102h PCL Program Counter's (PC) Least Significant byte 0000 0000 0000 0000 103h STATUS IRP(2) RP1 (2) RP0 TO PD Z DC C 000
MCP19111 TABLE 11-5: Addr MCP19111 SPECIAL REGISTERS SUMMARY BANK 3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Values on all other resets(1) Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 181h OPTION_REG RAPU INTEDG 1111 1111 1111 1111 IRP(2) RP1(2) T0CS T0SE PSA PS2 PS1 PS0 DC C 182h PCL 183h STATUS Program Counter's (PC) Least Significant byte 184h FSR 18
MCP19111 11.3.0.1 OPTION Register Note 1: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ of the OPTION register. See Section 23.1.
MCP19111 11.4 11.4.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 11-2 shows the two situations for loading the PC. The upper example in Figure 11-2 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH).
MCP19111 EXAMPLE 11-3: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE FIGURE 11-3: INDIRECT ADDRESSING 0x40 FSR INDF FSR FSR,7 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue DIRECT/INDIRECT ADDRESSING Direct Addressing RP1 RP0 6 Bank Select From Opcode Indirect Addressing 0 IRP 7 File Select Register Bank Select Location Select 00 01 10 0 Location Select 11 00h 180h Data Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memo
MCP19111 NOTES: DS22331A-page 78 2013 Microchip Technology Inc.
MCP19111 12.0 DEVICE CONFIGURATION Note: Device Configuration consists of Configuration Word, Code Protection and Device ID. 12.1 Configuration Word There are several Configuration Word bits that allow different timers to be enabled and memory protection options. These are implemented as Configuration Word at 2007h. REGISTER 12-1: The DBGEN bit in Configuration Word is managed automatically by device development tools, including debuggers and programmers.
MCP19111 12.2 Code Protection 12.4 Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting. 12.2.1 Four memory locations (2000h – 2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode.
MCP19111 13.0 OSCILLATOR MODES 13.3 The MCP19111 has one oscillator configuration which is an 8 MHz internal oscillator. 13.1 Internal Oscillator (INTOSC) The Internal Oscillator module provides a system clock source of 8 MHz. The frequency of the internal oscillator can be trimmed with a calibration value in the OSCTUNE register. 13.2 Frequency Tuning in User Mode In addition to the factory calibration, the base frequency can be tuned in the user's application.
MCP19111 13.3.1 OSCILLATOR DELAY UPON POWER-UP, WAKE-UP AND BASE FREQUENCY CHANGE On power up, the device is held in reset by the power-up time, if the power-up timer is enabled. In applications where the OSCTUNE register is used to shift the frequency of the internal oscillator, the application should not expect the frequency of the internal oscillator to stabilize immediately. In this case, the frequency may shift gradually toward the new value.
MCP19111 14.0 RESETS The reset logic is used to place the MCP19111 into a known state. The source of the reset can be determined by using the device status bits. There are multiple ways to reset this device: • • • • Power-on Reset (POR) Overtemperature Reset (OT) MCLR Reset WDT Reset To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a POR event.
MCP19111 TABLE 14-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR TO PD Condition 0 1 1 Power-on Reset u 0 u WDT Reset u 0 0 WDT Wake-up u u u MCLR Reset during normal operation u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x = unknown 14.1 Power-on Reset (POR) The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD.
MCP19111 14.3 Power-up Timer (PWRT) The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR Reset. The Power-up Timer operates from an internal RC oscillator. The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit (PWRTE), can disable (if set) or enable (if cleared or programmed) the Power-up Timer.
MCP19111 FIGURE 14-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TIOSCST OST Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) FIGURE 14-5: VDD MCLR Internal POR TPWRT PWRT Time-out TIOSCST OST Time-out Internal Reset DS22331A-page 86 2013 Microchip Technology Inc.
MCP19111 TABLE 14-3: INITIALIZATION CONDITION FOR REGISTERS Address Power-on Reset MCLR Reset WDT Reset Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h/ 100h/180h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/ 102h/182h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h/ 103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h/ 104h/184h xxxx xxxx uuuu uuuu uuuu uuuu
MCP19111 TABLE 14-3: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Address Power-on Reset MCLR Reset WDT Reset Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out (Continued) PIE1 87h -000 --00 -000 --00 -uuu --uu PIE2 88h 0-00 --00 0-00 --00 u-uu --uu APFCON 89h ---- ---0 ---- ---0 ---- ---u VINLVL 90h 0-xx xxxx 0-uu uuuu u-uu uuuu OCCON 91h 0xxx xxxx 0uuu uuuu uuuu uuuu CSGSCON 93h -xxx xxxx -uuu uuuu -uuu uuuu CSDGCON 95h 0--- xxxx 0---
MCP19111 TABLE 14-3: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Address Power-on Reset MCLR Reset WDT Reset Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out (Continued) PMDATH 195h --00 0000 --00 0000 --uu uuuu OSCCAL 198h -xxx xxxx -uuu uuuu -uuu uuuu DOVCAL 199h ---- xxxx ---- uuuu ---- uuuu TTACAL 19Ah ---- xxxx ---- uuuu ---- uuuu BGRCAL 19Bh ---- xxxx ---- uuuu ---- uuuu VROCAL 19Ch ---- xxxx ---- uuuu ---- uuuu ZROCAL 19Dh ---- x
MCP19111 14.8 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Over Temperature (OT) The PCON register bits are shown in Register 14-1.
MCP19111 15.
MCP19111 FIGURE 15-1: INTERRUPT LOGIC UVIF UVIE OVIF OVIE OCIF OCIE VINIF VINIE T0IF T0IE INTF INTE IOCF IOCE ADIF ADIE BCLIF BCLIE Wake-up (If in Sleep mode) Interrupt to CPU PEIF PEIE SSPIF SSPIE GIE TMR2IF TMR2IE TMR1IF TMR1IE FIGURE 15-2: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN (3) CLKOUT (4) INT pin (1) INTF flag (INTCON reg.) (1) (5) Interrupt Latency(2) GIE bit (INTCON reg.
MCP19111 15.3 Interrupt Control Registers 15.3.1 Note: INTCON REGISTER The INTCON register is a readable and writable register, that contains the various enable and flag bits for the TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 15-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register.
MCP19111 15.3.1.1 PIE1 Register The PIE1 register contains the Peripheral Interrupt Enable bits, as shown in Register 15-2. Note 1: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
MCP19111 15.3.1.2 PIE2 Register The PIE2 register contains the Peripheral Interrupt Enable bits, as shown in Register 15-3. Note 1: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
MCP19111 15.3.1.3 PIR1 Register The PIR1 register contains the Peripheral Interrupt Flag bits, as shown in Register 15-4. Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
MCP19111 15.3.1.4 PIR2 Register The PIR2 register contains the Peripheral Interrupt Flag bits, as shown in Register 15-5. Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
MCP19111 15.4 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Temporary holding registers W_TEMP and STATUS_TEMP should be placed in the last 16 bytes of GPR (see Figure 11-2). These 16 locations are common to all banks and do not require banking. This makes context save and restore operations simpler.
MCP19111 16.0 POWER-DOWN MODE (SLEEP) 16.1 Wake-up from Sleep The Power-Down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 1. 2. 3. 4. 5. 6. 7. 8. 9. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is not disabled.
MCP19111 16.1.
MCP19111 17.0 WATCHDOG TIMER (WDT) 17.2 The WDT has a nominal time-out period of 18 ms (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see Table 5-4). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The Watchdog Timer is a free running timer.
MCP19111 TABLE 17-1: WDT STATUS Conditions WDT WDTE = 0 CLRWDT Command Cleared Exit Sleep TABLE 17-2: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 OPTION_REG RAPU INTEDG T0CS T0SE PSA Bit 2 Bit 1 Bit 0 PS<2:0> Register on Page 75 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of all Configuration Word register bits.
MCP19111 18.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation (full VIN range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (see Registers 18-1 to 18-5).
MCP19111 18.
MCP19111 REGISTER 18-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 PMADRH<3:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 PMADRH<3:0>: Specifies the 4 Most Significant Address bits or High bits for Program Memory Reads.
MCP19111 18.3.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must write two bytes of the address to the PMADRL and PMADRH registers, and then set control bit RD (PMCON1<0>). Once the read control bit is set, the program memory Flash controller will use the second instruction cycle after to read the data. This causes the second instruction immediately following the “BSF PMCON1,RD” instruction to be ignored.
MCP19111 18.3.2 WRITING TO THE FLASH PROGRAM MEMORY A word of the Flash program memory may only be written to if the word is in an unprotected segment of memory, as defined in Section 12.1 “Configuration Word” (bits WRT1:WRT0). Note: The write protect bits are used to protect the users’ program from modification by the user’s code. They have no effect when programming is performed by ICSP.
MCP19111 FIGURE 18-2: BLOCK WRITES TO 4K FLASH PROGRAM MEMORY 7 5 0 07 PMDATH PMDATL 6 8 14 14 First word of block to be written 14 PMADRL<1:0> = 00 PMADRL<1:0> = 01 Buffer Register PMADRL<1:0> = 10 Buffer Register If at new row sixteen words of Flash are erased, then four buffers are transferred to Flash automatically after this word is written 14 PMADRL<1:0> = 11 Buffer Register Buffer Register Program Memory FIGURE 18-3: FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1
MCP19111 19.0 I/O PORTS In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has two registers for its operation. These registers are: • TRISx registers (data direction register) • PORTGPx registers (reads the levels on the pins of the device) Some ports may have one or more of the following additional registers.
MCP19111 19.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 19-1. For this device family, the following function can be moved between different pins.: This bit has no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected.
MCP19111 19.2.3 ANSELA REGISTER Analog input functions, such as ADC, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown in Table 19-1. The ANSELA register (Register 19-5) is used to configure the Input mode of an I/O pin to analog.
MCP19111 REGISTER 19-3: TRISGPA: PORTGPA TRI-STATE REGISTER R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TRISA<7:6>: PORTGPA Tri-State Control bit 1 = PORTGPA pin configured as an input (tri-stated) 0 = PORTGPA pin configured as an output bit 5 TRISA5: GPA5 Port Tri-St
MCP19111 REGISTER 19-5: ANSELA: ANALOG SELECT PORTGPA REGISTER U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — — ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 ANSA<3:0>: Analog Select PORTGPA Register bit 1 = Analog input. Pin is assigned as analog input.(1) 0 = Digital I/O.
MCP19111 19.3 PORTGPB and TRISGPB Registers PORTGPB is an 8-bit wide, bidirectional port consisting of seven general purpose I/O ports. The corresponding data direction register is TRISGPB (Register 19-7). Setting a TRISGPB bit (= 1) will make the corresponding PORTGPB pin an input (i.e., disable the output driver). Clearing a TRISGPB bit (= 0) will make the corresponding PORTGPB pin an output (i.e., enable the output driver). Example 19-1 shows how to initialize an I/O port. Input mode will be analog.
MCP19111 REGISTER 19-6: PORTGPB: PORTGPB REGISTER R/W-x R/W-x R/W-x R/W-x U-x R/W-x R/W-x R/W-x GPB7 GPB6 GPB5 GPB4 — GPB2 GPB1 GPB0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 GPB<7:4>: General Purpose I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL bit 3 Unimplemented: Read as ‘0’ bit 2-0 GPB<2:0>: General Purpose I/O Pin bit 1 = Port pin is > VIH 0 = Port
MCP19111 REGISTER 19-8: WPUGPB: WEAK PULL-UP PORTGPB REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 U-0 WPUB7 WPUB6 WPUB5 WPUB4 — WPUB2 WPUB1 — bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 WPUB<7:4>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘0’ bit 2-1 WPUB<2:1>: Weak Pull-up Register bit 1 = Pull-up enabled 0
MCP19111 TABLE 19-4: Name ANSELB APFCON OPTION_REG SUMMARY OF REGISTERS ASSOCIATED WITH PORTGPB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSB5 ANSB4 — ANSB2 ANSB1 — 116 — — — — — — — CLKSEL 110 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 75 PORTGPB GPB7 GPB6 GPB5 GPB4 — GPB2 GPB1 GPB0 115 TRISGPB TRISB7 TRISB6 TRISB5 TRISB4 — TRISB2 TRISB1 TRISB0 115 WPUB4 — WPUB2 WPUB1 — 116 WPUGPB Legend: WPUB7 — WPUB6 WPUB5 = unimple
MCP19111 NOTES: DS22331A-page 118 2013 Microchip Technology Inc.
MCP19111 20.0 INTERRUPT-ON-CHANGE Each PORTGPA and PORTGPB pin is individually configurable as an interrupt-on-change pin. Control bits IOCA and IOCB enable or disable the interrupt function for each pin. Refer to Register 20-1 and Register 20-2. The interrupt-on-change is disabled on a Power-on Reset. The interrupt-on-change on GPA5 is disabled when configured as MCLR pin in the Configuration Word.
MCP19111 20.5 Interrupt-On-Change Registers REGISTER 20-1: IOCA: INTERRUPT-ON-CHANGE PORTGPA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOCA7 IOCA6 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 IOCA<7:6>: Interrupt-on-Change PORTGPA Register bits. 1 = Interrupt-on-change enabled on the pin.
MCP19111 21.0 INTERNAL TEMPERATURE INDICATOR MODULE The MCP19111 is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit's range of the operating temperature falls between -40°C and +125°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. 21.
MCP19111 NOTES: DS22331A-page 122 2013 Microchip Technology Inc.
MCP19111 22.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The internal band gap supplies the voltage reference to the ADC. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit.
MCP19111 22.1 ADC Configuration When configuring and using the ADC, the following functions must be considered: • • • • • Port configuration Channel selection ADC conversion clock source Interrupt control Result formatting 22.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 19.0 “I/O Ports” for more information. Note: 22.1.
MCP19111 FIGURE 22-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b1 b2 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. 22.1.4 INTERRUPTS This interrupt can be generated while the device is operating, or while in Sleep.
MCP19111 22.2 22.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 22.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 22.2.5 “A/D Conversion Procedure”.
MCP19111 22.
MCP19111 REGISTER 22-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — ADCS2 ADCS1 ADCS0 — — — — bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = Reserved 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from internal oscillator with a divisor o
MCP19111 22.4 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 22-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 22-4.
MCP19111 FIGURE 22-4: ANALOG INPUT MODEL RS VA VDD Analog Input pin CPIN 5 pF Sampling Switch VT 0.6V RIC 1k VT 0.6V ILEAKAGE(1) SS RSS CHOLD = 10 pF VSS/VREF- 6V 5V VDD 4V 3V 2V Legend: CHOLD = Sample/Hold Capacitance CPIN = Input Capacitance RSS ILEAKAGE = Leakage current at the pin due to various junctions 5 6 7 8 91011 Sampling Switch (k) RIC = Interconnect Resistance RSS = Resistance of Sampling Switch SS = Sampling Switch VT = Threshold Voltage Note 1: Refer to Section 5.
MCP19111 TABLE 22-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 127 ADCON1 — ADCS2 ADCS1 ADCS0 — — — — 128 ADRESH — — — — — — ADRES9 ADRES8 128 ADRESL ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 128 ANSELA — — — — ANSA3 ANSA2 ANSA1 ANSA0 113 ANSELB — — ANSB5 ANSB4 — ANSB2 ANSB1 — 116 INTCON GIE PEIE T0IE INTE
MCP19111 NOTES: DS22331A-page 132 2013 Microchip Technology Inc.
MCP19111 23.0 TIMER0 MODULE The Timer0 module is an 8-bit timer/counter with the following features: • • • • • 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow Figure 23-1 is a block diagram of the Timer0 module.
MCP19111 23.1.4 23.1.5 SWITCHING PRESCALER BETWEEN TIMER0 AND WDT MODULES As a result of having the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changing the prescaler assignment from Timer0 to the WDT module, the instruction sequence shown in Example 23-1 must be executed. Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h.
MCP19111 24.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer with the following features: • • • • • 16-bit timer register pair (TMR1H:TMR1L) Readable and Writable (both registers) Selectable internal clock source 2-bit prescaler Interrupt on overflow Figure 24-1 is a block diagram of the Timer1 module.
MCP19111 24.3 Timer1 Prescaler 24.5 Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.
MCP19111 TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 93 PIE1 — ADIE BCLIE SSPIE — — TMR2IE TMR1IE 94 PIR1 — ADIF BCLIF SSPIF — — TMR2IF TMR1IF 96 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 135* TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 135* T1CON — — T1CK
MCP19111 25.0 TIMER2 MODULE The Timer2 module is an 8-bit timer with the following features: • • • • 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) See Figure 25-1 for a block diagram of Timer2. 25.1 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh.
MCP19111 25.
MCP19111 NOTES: DS22331A-page 140 2013 Microchip Technology Inc.
MCP19111 26.0 PWM MODULE The CCP module implemented on the MCP19111 is a modified version of the CCP module found in standard mid-range microcontrollers. In the MCP19111, the PWM module is used to generate the system clock or system oscillator. This system clock will control the MCP19111 switching frequency, as well as set the maximum allowable duty cycle. The PWM module does not continuously adjust the duty cycle to control the output voltage.
MCP19111 FIGURE 26-1: SIMPLIFIED PWM BLOCK DIAGRAM PWMRL PWMPHL 8 8 PWMPHH (SLAVE) PWMRH (SLAVE) LATCH DATA LATCH DATA 8 8 Comparator Comparator 8 R Q S Q OSC SYSTEM CLOCK 8 RESET TIMER TMR2 (Note 1) 8 Comparator 8 CLKPIN_IN PR2 Note 1: TIMER 2 should be clocked by FOSC (8 MHz). A PWM output (Figure 26-2) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 26-2: PWM OUTPUT 26.1.
MCP19111 26.1.4 PWM DUTY CYCLE (DCLOCK) 26.2 The PWM duty cycle (DCLOCK) is specified by writing to the PWMRL register. Up to 8-bit resolution is available. The following equation is used to calculate the PWM duty cycle (DCLOCK): Operation during Sleep When the device is placed in Sleep, the allocated timer will not increment and the state of the module will not change. If the CLKPIN pin is driving a value, it will continue to drive that value.
MCP19111 NOTES: DS22331A-page 144 2013 Microchip Technology Inc.
MCP19111 27.0 27.1 The I2C interface supports the following modes and features: MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE • • • • • • • • • • • • • Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module only operates in Inter-Integrated Circuit (I2C) mode.
MCP19111 FIGURE 27-2: MSSP BLOCK DIAGRAM (I2C SLAVE MODE) Internal Data Bus Read Write SSPBUF Reg SCL Shift Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect Addr Match SSPADD Reg Start and Stop bit Detect 27.2 I2C MODE OVERVIEW The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment, where the master devices initiate the communication. A Slave device is controlled through addressing.
MCP19111 The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero; letting the line float is considered a logical one. Before selecting any I2C mode, the SCL and SDA pins must be programmed to inputs by setting the appropriate TRIS bits.
MCP19111 27.2.1 CLOCK STRETCHING When a slave device has not completed processing data, it can delay the transfer of more data through the process of Clock Stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released.
MCP19111 27.3.4 SDA HOLD TIME The hold time of the SDA pin is selected by the SDAHT bit of the SSPCON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. TABLE 27-1: I2C BUS TERMS TERM Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus.
MCP19111 27.3.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. These bits will have no effect on slave modes where interrupt on Start and Stop detect are already enabled.
MCP19111 27.4 I2C SLAVE MODE OPERATION The MSSP Slave mode operates in one of the four modes selected in the SSPM bits of SSPCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing mode operate the same as 7-bit, with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operate the same as the other modes. The exception is the SSPIF bit getting set upon detection of a Start, Restart or Stop condition. 27.4.
MCP19111 27.4.3.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C Slave in 7-bit Addressing mode, all decisions made by hardware or software and their effect on reception. Figure 27-6 and Figure 27-7 are used as a visual reference for this description. This is a step-by-step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected.
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Bus Master sends Stop condition Receive Address SDA SCL S Receive Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 R/W=0 ACK 8 9 SEN Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 SEN ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Clock is held low until CKP is set to ‘1’ SSPIF Cleared by software BF SSPBUF is read Cleared by software SSPIF set on 9th falling edge of SCL First byte of data is available in SSPBUF SSPOV SSPOV set because
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R/W = 0 Receiving Address SDA Master sends Stop condition Master releases SDA to slave for ACK sequence Receive Data ACK A7 A6 A5 A4 A3 A2 A1 ACK SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 ACK Receive Data D7 D6 D5 D4 D3 D2 D1 D0 8 9 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P SSPIF No interrupt after if not ACK from Slave Cleared by software BF Received address is loaded into SSPBUF Received data is available on SSPBUF ACKDT Slave software clears ACKDT to ACK the received
MCP19111 27.4.4 SLAVE TRANSMISSION 27.4.4.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission.
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) Master sends Stop condition Receiving Address SDA Transmitting Data Automatic ACK A7 A6 A5 A4 A3 A2 A1 R/W = 1 Automatic ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data 1 8 1 1 SCL 2 3 4 5 6 7 9 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 S SSPIF Cleared by software BF Received address is read from SSPBUF Data to transmit is loaded into SSPBUF BF is automatically cleared after 8th falling edge of SCL CKP Whe
MCP19111 27.4.4.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure 27-11 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle.
Master sends Stop condition Master releases SDAx to slave for ACK sequence Receiving Address SDA ACK A7 A6 A5 A4 A3 A2 A1 SCL S 1 2 3 4 5 6 Automatic R/W = 1 7 8 9 Transmitting Data Automatic ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 2 3 4 5 6 7 8 9 Transmitting Data 2 3 4 5 6 7 Cleared by software BF Received address is read from SSPBUF Data to transmit is loaded into SSPBUF BF is automatically cleared after 8th falling edge of SCL ACKDT Slave clears AC
MCP19111 27.4.5 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSP module configured as an I2C Slave in 10-bit Addressing mode. Figure 27-12 is used as a visual reference for this description. This is a step-by-step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSPSTAT is set; SSPIF is set, if interrupt on Start detect is enabled.
Master sends Stop condition Receive Second Address Byte Receive First Address Byte SDA SCL 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 ACK 8 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 9 Receive Data Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 S SCL is held low while CKP = 0 SSPIF Set by hardware on 9th falling edge Cleared by software If address matches SSPADD it is loaded into SSPBUF Receive address is read fr
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Master sends Restart event Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK SDA SCL S 1 2 3 4 5 6 7 8 9 Master sends not ACK Receiving Second Address Byte Receive First Address Byte A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 8 1 9 2 3 4 5 6 7 8 Transmitting Data Byte ACK 9 ACK = 1 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 Sr SSPIF Set by hardware Cleared by software Set by hardware BF SSPBUF loaded with received address Received address is read from
MCP19111 27.4.7 CLOCK STRETCHING 27.4.7.2 Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching, as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL.
MCP19111 27.4.9 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in the 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address, which can address all devices.
MCP19111 27.5 I2C Master Mode 27.5.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPCON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary, to drive the pins low. The master device generates all of the serial clock pulses and the Start and Stop conditions.
MCP19111 FIGURE 27-17: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX ‚ – 1 SCL allowed to transition high SCL deasserted but slave holds SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 27.5.
MCP19111 27.5.5 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit of the SSPCON2 register is programmed high and the Master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting.
MCP19111 27.5.6 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and will allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG).
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MCP19111 27.5.7 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSPCON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set, or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-tolow/low-to-high) and data is shifted into the SSPSR.
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MCP19111 27.5.8 ACKNOWLEDGE SEQUENCE TIMING 27.5.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the 9th clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
MCP19111 27.5.10 SLEEP OPERATION 27.5.13 2 While in Sleep mode, the I C slave module can receive addresses or data, and when an address match or complete byte transfer occurs, wakes the processor from Sleep (if the MSSP interrupt is enabled). 27.5.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 27.5.
MCP19111 27.5.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the Start condition (Figure 27-25). SCL is sampled low before SDA is asserted low (Figure 27-26). b) During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 27-27).
MCP19111 FIGURE 27-26: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA SCL Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
MCP19111 27.5.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 27-28). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
MCP19111 27.5.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 27-30).
MCP19111 TABLE 27-1: SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 93 PIE1 — ADIE BCLIE SSPIE — — TMR2IE TMR1IE 94 PIR1 — ADIF BCLIF SSPIF — — TMR2IF TMR1IF 96 TRISGPA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 112 TRISGPB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 115 SSPADD ADD7 ADD6 ADD5 AD
MCP19111 27.6 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in I2C Master mode. The Baud Rate Generator (BRG) reload value is placed in the SSPADD register (Register 27-7). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state.
MCP19111 REGISTER 27-2: SSPSTAT: SSP STATUS REGISTER R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Data Input Sample bit 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: Clock Edge Select bit 1
MCP19111 REGISTER 27-3: SSPCON1: SSP CONTROL REGISTER 1 R/C/HS-0 R/C/HS-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP R/W-0 R/W-0 R/W-0 R/W-0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No c
MCP19111 REGISTER 27-4: SSPCON2: SSP CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the S
MCP19111 REGISTER 27-5: SSPCON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(2) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on the 8th falling edge of SCL clock
MCP19111 REGISTER 27-6: SSPMSK: SSP MASK REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Sla
MCP19111 REGISTER 27-8: SSPMSK2: SSP MASK REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK2<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 MSK2<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD2 to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK2<0>: Mask bit for I2
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MCP19111 28.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) 28.1 Common Programming Interfaces Connection to a target device is typically done through an ICSP header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6 pin, 6 connector) configuration. See Figure 28-1. ICSP programming allows customers to manufacture circuit boards with unprogrammed devices.
MCP19111 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices, such as resistors, diodes, or even jumpers. See Figure 28-3 for more information.
MCP19111 29.0 INSTRUCTION SET SUMMARY The MCP19111 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each instruction is a 14-bit word divided into an opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction.
MCP19111 TABLE 29-2: MCP19111 INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affecte d Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move
MCP19111 29.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: (W) + k (W) Status Affected: Description: BCF k Bit Clear f Syntax: [ label ] BCF Operands: 0 f 127 0b7 C, DC, Z Operation: 0 (f) The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.
MCP19111 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 f 127 0b<7 Operands: None Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
MCP19111 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
MCP19111 MOVF Move f Syntax: [ label ] Operands: 0 f 127 d [0,1] MOVF f,d MOVWF Move W to f Syntax: [ label ] MOVWF Operands: 0 f 127 Operation: (W) (f) f Operation: (f) (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’. If d = 0, destination is W register. If d = 1, the destination is file register ‘f’ itself.
MCP19111 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] RETFIE RETLW k Operands: None Operands: 0 k 255 Operation: TOS PC, 1 GIE Operation: k (W); TOS PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
MCP19111 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 f 127 d [0,1] RLF f,d Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
MCP19111 SUBWF Subtract W from f XORWF Exclusive OR W with f Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORWF Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - (W) destination) Operation: (W) .XOR. (f) destination) Status Affected: C, DC, Z Status Affected: Z Description: Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
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MCP19111 30.
MCP19111 30.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 30.
MCP19111 30.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
MCP19111 30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
MCP19111 31.0 PACKAGING INFORMATION 31.1 Package Marking Information 28-Lead QFN (5x5x0.9 mm) PIN 1 Example PIN 1 19111 e3 E/MQ ^^ 1246256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free.
MCP19111 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22331A-page 206 2013 Microchip Technology Inc.
MCP19111 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc.
MCP19111 28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5 mm Body [QFN] Land Pattern With 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-2140A DS22331A-page 208 2013 Microchip Technology Inc.
MCP19111 APPENDIX A: REVISION HISTORY Revision A (January 2013) • Original Release of this Document. 2013 Microchip Technology Inc.
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MCP19111 INDEX A Block Diagrams MCP19111.................................................. 8 A/D C Specifications.......................................................... 3, 31 A/D Conversion ................................................................. 125 Requirements.............................................................. 32 Timing ................................................................... 32, 33 Absolute Maximum Ratings ................................................
MCP19111 F Features Microcontroller .............................................................. 1 Miscellaneous ............................................................. 19 Protection .................................................................... 18 Synchronous Buck ........................................................ 1 Firmware Instructions........................................................ 191 Flash Program Memory Control ........................................
MCP19111 M P MASTER Error Signal Gain ................................................ 43 Master Synchronous Serial Port. See MSSPx MCLR .................................................................................. 84 Internal ........................................................................ 84 Memory Organization.......................................................... 67 Data ............................................................................ 68 Program ............................
MCP19111 R Reader Response ............................................................. 218 Read-Modify-Write Operations.......................................... 191 Register OVFCON (Output Voltage Set Point Fine Control) ..... 45 Registers ABECON (Analog Block Enable Control).................... 50 ADCON0 (ADC Control 0) ........................................ 127 ADCON1 (ADC Control 1) ........................................ 128 ADRESH (ADC Result High) with ADFM = 0)...........
MCP19111 T T1CON Register ............................................................... 136 T1CKPS1:T1CKPS0 Bits ............................................ 44 Temperature Indicator Module .......................................... 121 Thermal Specifications........................................................ 26 Timer Requirements RESET, Watchdog Timer, Oscillator Start-up Timer and Power-up ............................................................ 30 Timer0 .......................................
MCP19111 NOTES: DS22331A-page 216 2013 Microchip Technology Inc.
MCP19111 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
MCP19111 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
MCP19111 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
MCP19111 NOTICE TO CUSTOMERS This product is subject to a license from Power-One®, Inc. related to digital power technology (DPT) patents owned by Power-One, Inc. This license does not extend to stand-alone power supply products. DS22331A-page 220 2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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