Datasheet

MCP1754/MCP1754S
DS20002276C-page 18  2011-2013 Microchip Technology Inc.
4.4 Input Capacitor
Low input source impedance is necessary for the LDO
output to operate properly. When operating from
batteries or in applications with long lead length
(>10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF is recommended for most
applications.
For applications that have output step load
requirements, the input capacitance of the LDO is very
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from in order to respond quickly to
the output load step. For good step response
performance, the input capacitor should be of
equivalent or higher value than the output capacitor.
The capacitor should be placed as close to the input of
the LDO as is practical. Larger input capacitors also
help reduce any high-frequency noise on the input and
output of the LDO and reduce the effects of any
inductance that exists between the input source
voltage and the input capacitance of the LDO.
4.5 Power Good Output (PWRGD)
The open-drain PWRGD output is used to indicate
when the output voltage of the LDO is within 94%
(typical value, see Section 1.0 “Electrical
Characteristics” for minimum and maximum
specifications) of its nominal regulation value.
As the output voltage of the LDO rises, the open-drain
PWRGD output is actively held low until the output
voltage has exceeded the power good threshold plus
the hysteresis value. Once this threshold has been
exceeded, the power good time delay is started (shown
as T
PG
in the Electrical Characteristics table). The
power good time delay is fixed at 100 µs (typical). After
the time delay period, the PWRGD open-drain output
becomes inactive and may be pulled high by an
external pull-up resistor, indicating that the output
voltage is stable and within regulation limits. The power
good output is typically pulled up to V
IN
or V
OUT
. Pulling
the signal up to V
OUT
conserves power during
Shutdown mode.
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circuitry has a 200 µs delay when
detecting a falling output voltage, which helps to
increase noise immunity and avoid false triggering of
the power good output during fast output transients.
See Figure 4-2 for power good timing characteristics.
When the LDO is put into Shutdown mode using the
SHDN
input, the power good output is pulled low
immediately, indicating that the output voltage is out of
regulation. The timing diagram for the power good
output when using the shutdown input is shown in
Figure 4-3.
The power good output is an open-drain output that can
be pulled up to any voltage equal to or less than the
LDO input voltage. This output is capable of sinking
5mA (V
PWRGD
< 0.4V).
FIGURE 4-2: Power Good Timing.
FIGURE 4-3: Power Good Timing from
Shutdown.
4.6 Shutdown Input (SHDN)
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN
threshold is a fixed
voltage level. The minimum value of this shutdown
threshold required to turn the output ON is 2.4V. The
maximum value required to turn the output OFF is 0.8V.
TPG
TVDET_PWRGD
VPWRGD_TH
VOUT
PWRGD
VOL
VOH
V
IN
SHDN
V
OUT
T
DELAY_SHDN
PWRGD
T
PG