Datasheet

 2011-2013 Microchip Technology Inc. DS20002276C-page 15
MCP1754/MCP1754S
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1 and Table 3-2.
3.1 Regulated Output Voltage (V
OUT
)
Connect V
OUT
to the positive side of the load and the
positive terminal of the output capacitor. The positive
side of the output capacitor should be physically
located as close to the LDO V
OUT
pin as is practical.
The current flowing out of this pin is equal to the DC
load current.
3.2 Power Good Output (PWRGD)
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
threshold has a typical hysteresis value of 2%. The
PWRGD output is delayed by 100 µs (typical) from the
time the LDO output is within 92% + 2% (typical
hysteresis) of the regulated output value on power-up.
This delay time is internally fixed. The PWRGD pin may
be pulled up to V
IN
or V
OUT
. Pulling up to V
OUT
conserves power when the device is in shutdown
(S
HDN = 0V) mode.
3.3 Ground Terminal (GND)
Regulator ground. Tie GND to the negative side of the
output and the negative side of the input capacitor.
Only the LDO bias current flows out of this pin; there is
no high current. The LDO output regulation is
referenced to this pin. Minimize the voltage drops
between this pin and the negative side of the load.
3.4 Shutdown Input (SHDN)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN
input is at a logic high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic low level, the LDO
output voltage is disabled. When the SHDN
input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state.
3.5 Unregulated Input Voltage (V
IN
)
Connect V
IN
to the input unregulated source voltage.
Like all low dropout linear regulators, low-source
impedance is necessary for the stable operation of the
LDO. The amount of capacitance required to ensure
low-source impedance depends on the proximity of the
input source capacitors or battery type. For most
applications, 1 µF of capacitance ensures stable
operation of the LDO circuit. The input capacitor should
have a capacitance value equal to or larger than the
output capacitor for performance applications. The
input capacitor supplies the load current during
transients and improves performance. For applications
that have load currents below 10 mA, the input
capacitance requirement can be lowered. The type of
capacitor used may be ceramic, tantalum or aluminum
electrolytic. The low ESR characteristics of the ceramic
yields better noise and PSRR performance at high
frequency.
TABLE 3-1: MCP1754 PIN FUNCTION TABLE
Pin No.
SOT223-5
Pin No.
SOT23-5
Pin No.
2X3 DFN
Name Function
451V
OUT
Regulated Voltage Output
5 4 2 PWRGD Open-Drain Power Good Output
——3,6,7 NC No Connection
3 2 4 GND Ground Terminal
1 3 5 SHDN
Shutdown Input
218V
IN
Unregulated Supply Voltage
EP — EP GND Exposed Pad, Connected to GND
TABLE 3-2: MCP1754S PIN FUNCTION TABLE
Pin No.
SOT223-3
Pin No.
SOT23A
Pin No.
SOT89
Pin No.
2X3 DFN
Name Function
3231V
OUT
Regulated Voltage Output
———2,3,5,6,7 NC No Connection
2 1 2 4 GND Ground Terminal
1318V
IN
Unregulated Supply Voltage
EP — EP EP GND Exposed Pad, Connected to GND