Datasheet

MCP1727
DS21999B-page 22 © 2007 Microchip Technology Inc.
5.3.1.2 Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
As you can see from the result, this application will be
operating very near the maximum operating junction
temperature of 125°C. The PCB layout for this
application is very important as it has a significant
impact on the junction-to-ambient thermal resistance
(Rθ
JA
) of the 3x3 DFN package, which is very important
in this application.
5.3.1.3 Maximum Package Power
Dissipation at 60°C Ambient
Temperature
From this table, you can see the difference in maximum
allowable power dissipation between the 3x3 DFN
package and the 8-pin SOIC package. This difference
is due to the exposed metal tab on the bottom of the
DFN package. The exposed tab of the DFN package
provides a very good thermal path from the die of the
LDO to the PCB. The PCB then acts like a heatsink,
providing more area to distribute the heat generated by
the LDO.
5.4 C
DELAY
Calculations (typical)
T
J
=T
JRISE
+ T
A(MAX)
T
J
= 63.14°C + 60.0°C
T
J
= 123.14°C
3x3DFN (41° C/W Rθ
JA
):
P
D(MAX)
= (125°C – 60°C) / 41° C/W
P
D(MAX)
= 1.585W
SOIC8 (150°C/Watt Rθ
JA
):
P
D(MAX)
= (125°C – 60°C)/ 150° C/W
P
D(MAX)
= 0.433W
CI
ΔT
ΔV
-------
•=
Where:
C=C
DELAY
Capacitor
I=C
DELAY
charging current,
140 nA typical.
ΔT = time delay
ΔV=C
DELAY
threshold voltage,
0.42V typical
CI
ΔT
ΔV
-------
•
140nA ΔT•()
0.42V
---------------------------------- 333.3
09–
×10 ΔT•== =
For a delay of 300 ms:
C = 333.3E-09 * .300
C = 100E-09uF (0.1 μF)