Datasheet

MCP1727
DS21999B-page 14 © 2007 Microchip Technology Inc.
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Input Voltage Supply (V
IN
)
Connect the unregulated or regulated input voltage
source to V
IN
. If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications.
3.2 Shutdown Control Input (SHDN)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN
input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 µA.
3.3 Ground (GND)
Connect the GND pin of the LDO to a quiet circuit
ground. This will help the LDO power supply rejection
ratio and noise performance. The ground pin of the
LDO only conducts the quiescent current of the LDO
(typically 120 µA), so a heavy trace is not required.
For applications have switching or noisy inputs tie the
GND pin to the return of the output capacitor. Ground
planes help lower inductance and voltage spikes
caused by fast transient load currents and are
recommended for applications that are subjected to
fast load transients.
3.4 Power Good Output (PWRGD)
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
threshold has a typical hysteresis value of 2%. The
PWRGD output is typically delayed by 200 µs (typical,
no capacitance on C
DELAY
pin) from the time the LDO
output is within 92% + 3% (max hysteresis) of the
regulated output value on power-up. This delay time is
controlled by the C
DELAY
pin.
3.5 Power Good Delay Set-Point Input
(C
DELAY
)
The C
DELAY
input sets the power-up delay time for the
PWRGD output. By connecting an external capacitor
from the C
DELAY
pin to ground, the typical delay times
for the PWRGD output can be adjusted from 200 µs (no
capacitance) to 300 ms (0.1 µF capacitor). This allows
for the optimal setting of the system reset time.
3.6 Output Voltage Sense/Adjust Input
(ADJ/Sense)
3.6.1 ADJ
For adjustable applications, the output voltage is
connected to the ADJ input through a resistor divider
that sets the output voltage regulation value. This
provides the user the capability to set the output
voltage to any value they desire within the 0.8V to 5.0V
range of the device.
Fixed Output
Adjustable
Output
Name Description
11V
IN
Input Voltage Supply
22V
IN
Input Voltage Supply
3 3 SHDN
Shutdown Control Input (active-low)
4 4 GND Ground
5 5 PWRGD Power Good Output (open-drain)
66C
DELAY
Power Good Delay Set-Point Input
—
7 ADJ Voltage Sense Input (adjustable version)
7
—
Sense Voltage Sense Input (fixed voltage version)
88V
OUT
Regulated Output Voltage
Exposed Pad Exposed Pad EP Exposed Pad of the DFN Package (ground potential)