Datasheet

© 2007 Microchip Technology Inc. DS21936C-page 13
MCP1726
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Input Voltage Supply (V
IN
)
Connect the unregulated or regulated input voltage
source to V
IN
. If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications.
3.2 Shutdown Control Input (SHDN)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN
input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 µA.
3.3 Ground (GND)
Connect the GND pin of the LDO to a quiet circuit
ground. This will help the LDO power supply rejection
ratio and noise performance. The ground pin of the
LDO only conducts the quiescent current of the LDO
(typically 140 µA), so a heavy trace is not required.
3.4 Power Good Output (PWRGD)
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
output has a typical hysteresis value of 2% for the
adjustable voltage version and for voltage outputs less
than 2.5V. For fixed output voltage versions greater
than 2.5V, the hysteresis is 0.7%. The PWRGD output
is delayed on power-up by 200 µs (typical, no capaci-
tance on C
DELAY
pin). This delay time is controlled by
the C
DELAY
pin.
3.5 Power Good Delay Set-Point Input
(C
DELAY
)
The C
DELAY
input sets the power-up delay time for the
PWRGD output. By connecting an external capacitor
from the C
DELAY
pin to ground, the delay times for the
PWRGD output can be adjusted from 200 µs (no
capacitance) to 300 ms (0.1 µF capacitor). This allows
for the optimal setting of the system reset time.
3.6 Output Voltage Sense Input (ADJ)
The output voltage adjust pin (ADJ) for the adjustable
output voltage version of the MCP1726 allows the user
to set the output voltage of the LDO by using two
external resistors. The adjust pin voltage is 0.41V
(typical).
3.7 Regulated Output Voltage (V
OUT
)
The V
OUT
pin(s) is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1726 is stable with
ceramic, tantalum and aluminum-electrolytic capaci-
tors. See Section 4.3 “Output Capacitor” for output
capacitor selection guidance.
3.8 Exposed Pad (EP)
The 3x3 DFN package has an exposed pad on the bot-
tom of the package. This pad should be soldered to the
Printed Circuit Board (PCB) to aid in the removal of
heat from the package during operation. The exposed
pad is at the ground potential of the LDO.
Pin No.
Fixed Output
Pin No.
Adjustable
Output
Name Description
11V
IN
Input Voltage Supply
22V
IN
Input Voltage Supply
3 3 SHDN
Shutdown Control Input (active-low)
4 4 GND Ground
5 5 PWRGD Power Good Output
66C
DELAY
Power Good Delay Set-Point Input
— 7 ADJ Output Voltage Sense Input (adjustable version)
7
— V
OUT
Regulated Output Voltage
88V
OUT
Regulated Output Voltage
Exposed Pad Exposed Pad EP Exposed Pad of the DFN Package