Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: Rise Time vs. Supply Voltage.
- FIGURE 2-2: Rise Time vs. Capacitive Load.
- FIGURE 2-3: Rise and Fall Times vs. Temperature.
- FIGURE 2-4: Fall Time vs. Supply Voltage.
- FIGURE 2-5: Fall Time vs. Capacitive Load.
- FIGURE 2-6: Propagation Delay vs. Input Amplitude.
- FIGURE 2-7: Propagation Delay Time vs. Supply Voltage.
- FIGURE 2-8: Propagation Delay Time vs. Temperature.
- FIGURE 2-9: Quiescent Current vs. Supply Voltage.
- FIGURE 2-10: Quiescent Current vs. Temperature.
- FIGURE 2-11: Output Resistance (Output High) vs. Supply Voltage.
- FIGURE 2-12: Output Resistance (Output Low) vs. Temperature.
- FIGURE 2-13: Supply Current vs. Capacitive Load.
- FIGURE 2-14: Supply Current vs. Capacitive Load.
- FIGURE 2-15: Supply Current vs. Capacitive Load.
- FIGURE 2-16: Supply Current vs. Frequency.
- FIGURE 2-17: Supply Current vs. Frequency.
- FIGURE 2-18: Supply Current vs. Frequency.
- FIGURE 2-19: Crossover Energy vs. Supply Voltage.
- 3.0 Pin Descriptions
- 4.0 Application Information
- 5.0 Packaging Information

© 2007 Microchip Technology Inc. DS22022B-page 9
MCP1403/4/5
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
(1)
3.1 Supply Input (V
DD
)
V
DD
is the bias supply input for the MOSFET driver and
has a voltage range of 4.5V to 18V. This input must be
decoupled to ground with a local capacitor. This bypass
capacitor provides a localized low-impedance path for
the peak currents that are to be provided to the load.
3.2 Control Inputs A and B
The MOSFET driver input is a high-impedance, TTL/
CMOS-compatible input. The input also has hysteresis
between the high and low input levels, allowing them to
be driven from slow rising and falling signals, and to
provide noise immunity.
3.3 Ground (GND)
Ground is the device return pin. The ground pin should
have a low impedance connection to the bias supply
source return. High peak currents will flow out the
ground pin when the capacitive load is being
discharged.
3.4 Outputs A and B
Outputs A and B are CMOS push-pull output that is
capable of sourcing and sinking 4.5A of peak current
(V
DD
= 18V). The low output impedance ensures the
gate of the external MOSFET will stay in the intended
state even during large transients. These output also
has a reverse current latch-up rating of 1.5A.
3.5 Exposed Metal Pad
The exposed metal pad of the DFN package is not
internally connected to any potential. Therefore, this
pad can be connected to a ground plane or other
copper plane on a printed circuit board to aid in heat
removal from the package.
8-Pin
PDIP
SOIC
8-Pin
DFN
16-Pin
SOIC
Symbol Description
1 1 1 NC No Connection
2 2 2 IN A Control Input for Output A
— — 3 NC No Connection
3 3 4 GND Ground
— — 5 GND Ground
— — 6 NC No Connection
4 4 7 IN B Control Input for Output B
— — 8 NC No Connection
— — 9 NC No Connection
5 5 10 OUT B Output B
— — 11 OUT B Output B
6612V
DD
Supply Input
——13V
DD
Supply Input
7 7 14 OUT A Output A
— — 15 OUT A Output A
8 8 16 NC No Connection
— PAD — NC Exposed Metal Pad
Note 1: Duplicate pins must be connected for proper operation.