Datasheet
Table Of Contents
- Device Features
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- 3.0 PIN Description
- 4.0 Operational Description
- 5.0 Application Information
- 5.1 Supply Monitor Noise Sensitivity
- 5.2 Conventional Voltage Monitoring
- 5.3 Using in PIC® Microcontroller, ICSP™ Applications
- 5.4 Modifying The Trip Point, VTRIP
- 5.5 MOSFET Low-Drive Protection
- 5.6 Low-Power Applications
- 5.7 Controllers and Processors With Bidirectional I/O Pins
- 5.8 RESET Signal Integrity During Power-Down
- 6.0 Standard Device Offerings
- 7.0 Development Tools
- 8.0 Packaging Information
- Appendix A: Revision History
- Product Identification System
- Trademarks
- Worldwide Sales and Service

MCP131X/2X
DS21985D-page 32 2005-2012 Microchip Technology Inc.
4.2 Reset Delay Timer (t
RST
)
The Reset delay timer ensures that the MCP131X/2X
device will “hold” the embedded system in Reset until
the system voltage has stabilized. There are several
time-out options to better meet the requirements of
different applications. These Reset delay timer time-
outs are shown in Table 4-2. The Standard offering
time-out is typically 200 ms.
The Reset delay timer (t
RST
) starts after the device volt-
age rises above the “actual” trip point (V
TRIP
) plus the
hysteresis (V
HYS
). When the Reset delay timer times-
out, the Reset output pin (RST/RST
) is driven inactive.
TABLE 4-2: RESET DELAY TIMER
TIME OUTS
(1)
Figure 4-15 illustrates when the Reset delay timer
(t
RST
) is active or inactive.
FIGURE 4-15: Reset Power-up Timer
Waveform.
4.2.1 EFFECT OF TEMPERATURE ON
RESET POWER-UP TIMER (T
RPU
)
The Reset delay timer time-out period (t
RST
)
determines how long the device remains in the Reset
condition. This time-out is affected by both the device
V
DD
and temperature. Typical responses for different
V
DD
values and temperatures are shown in Figures 2-
33, 2-32 and 2-31.
Note: While the Reset delay timer (t
RST
) is
active, additional system current is con-
sumed.
t
RST
Units
Min Typ Max
1.0 1.4 2.0 ms
20 30 40 ms
140 200 280 ms
1120 1.6 2.24 sec
This is the
minimum time that
the Reset delay
timer will “hold” the
Reset pin active
after V
DD
rises
above
V
TRIP
+ V
HYS
This is the
maximum time
that the Reset
delay timer will
“hold” the Reset
pin active after
V
DD
rises above
V
TRIP
+ V
HYS
Note 1: Shaded rows are custom ordered time
outs.
V
TRIP
V
DD
RST
t
RST
Reset Delay
Timer Inactive
Reset
Delay
Timer
Inactive
Reset Delay
Timer Active
See Figures 2-12,
2-10 and 2-11
See Figures 2-15,
2-14 and 2-13
See Figures 2-12,
2-10 and 2-11