Datasheet

dsPIC33FJ32GP10X and dsPIC33FJ32MC10X
DS80548A-page 2  2012 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Number
Issue Summary
Affected
Revisions
(1)
A0
SPI Frame Sync
Pulse
1. Frame sync pulse is not generated in Master mode when
FRMPOL = 0.
X
SPI Frame Sync
Pulse
2. When in SPI Slave mode, with the frame sync pulse set as an
input, FRMDLY must be set to ‘0’.
X
UART TX Interrupt 3. A TX interrupt may occur before the data transmission is
complete.
X
UART UARTEN 4. The Transmitter Write Pointer does not clear when the UART
is disabled (UARTEN = 0); it requires UTXEN to be set in
order to clear the Write Pointer.
X
CPU div.sd
Instruction
5. When using the div.sd instruction, the overflow bit is not
getting set when an overflow occurs.
X
CPU Interrupt
Disable
6. When a previous DISI instruction is active (i.e., the DISICNT
register is non-zero), and the value of the DISICNT register is
updated manually, the DISICNT register Freezes and disables
interrupts permanently.
X
Oscillator Clock
Switching
7. Clock switch does not abort when device enters Sleep mode. X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.