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 2012 Microchip Technology Inc. DS80548A-page 1

dsPIC33FJ32GP10X and

dsPIC33FJ32MC10X

The dsPIC33FJ32GP10X and dsPIC33FJ32MC10X

family devices that you have received conform

functionally to the current Device Data Sheet

(DS70652D), except for the anomalies described in this

document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the dsPIC33FJ32GP10X and

dsPIC33FJ32MC10X silicon.

Data Sheet clarifications and corrections start on Page 5,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 3 or

PICkit™ 3:

1. Using the appropriate interface, connect the device

to the MPLAB ICD 3 programmer/debugger or

PICkit 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device

, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Select Tool

4. Perform a “Connect” operation to the device

(Debugger>Connect

). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The Device and Revision ID values for the various

dsPIC33FJ32GP10X and dsPIC33FJ32MC10X silicon

revisions are shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A0).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

dsPIC33FJ32GP101 0x0A00

0x3000

dsPIC33FJ32GP102 0x0A01

dsPIC33FJ32GP104 0x0A03

dsPIC33FJ32MC101 0x0A04

dsPIC33FJ32MC102 0x0A05

dsPIC33FJ32MC104 0x0A07

Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in

program memory.

2: Refer to the “dsPIC33F Flash Programming Specification for Devices with Volatile Configuration Bits”

(DS70659) for detailed information on Device and Revision IDs for your specific device.

dsPIC33FJ32GP10X and dsPIC33FJ32MC10X Family Silicon

Errata and Data Sheet Clarification

Summary of content (8 pages)

PAGE 1
dsPIC33FJ32GP10X and dsPIC33FJ32MC10X dsPIC33FJ32GP10X and dsPIC33FJ32MC10X Family Silicon Errata and Data Sheet Clarification The dsPIC33FJ32GP10X and dsPIC33FJ32MC10X family devices that you have received conform functionally to the current Device Data Sheet (DS70652D), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 3 or PICkit™ 3: 1.
PAGE 2
dsPIC33FJ32GP10X and dsPIC33FJ32MC10X TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A0 SPI Frame Sync Pulse 1. Frame sync pulse is not generated in Master mode when FRMPOL = 0. X SPI Frame Sync Pulse 2. When in SPI Slave mode, with the frame sync pulse set as an input, FRMDLY must be set to ‘0’. X UART TX Interrupt 3. A TX interrupt may occur before the data transmission is complete. X UART UARTEN 4.
PAGE 3
dsPIC33FJ32GP10X and dsPIC33FJ32MC10X Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A0). 3.
PAGE 4
dsPIC33FJ32GP10X and dsPIC33FJ32MC10X 5. Module: CPU 7. Module: Oscillator When using the Signed 32 by 16-bit Division instruction, div.sd, the overflow bit does not always get set when an overflow occurs. Clock switch requests are not aborted if the device enters Sleep mode during the execution of the clock switch. Work around Work around Test for and handle overflow conditions outside of the div.sd instruction. None. Affected Silicon Revisions A0 Affected Silicon Revisions A0 X X 6.
PAGE 5
dsPIC33FJ32GP10X and dsPIC33FJ32MC10X Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS70652D): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. None to report at this time.  2012 Microchip Technology Inc.
PAGE 6
dsPIC33FJ32GP10X and dsPIC33FJ32MC10X APPENDIX A: REVISION HISTORY Rev A Document (8/2012) Initial release of this document, issued for Revision A0 silicon. Includes silicon issues 1 and 2 (SPI), 3 and 4 (UART), 5 and 6 (CPU), and 7 (Oscillator). DS80548A-page 6  2012 Microchip Technology Inc.
PAGE 7
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 8
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