Datasheet

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70000652F-page 92  2011-2014 Microchip Technology Inc.
6.3 POR
A POR circuit ensures the device is reset from power-
on. The POR circuit is active until V
DD crosses the
V
POR threshold and the delay, TPOR, has elapsed. The
delay, T
POR, ensures that the internal device bias
circuits become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate require-
ments to generate the POR. Refer to Section 26.0
“Electrical Characteristics” for details.
The Power-on Reset (POR) status bit in the Reset Con-
trol (RCON<0>) register is set to indicate the Power-on
Reset.
6.4 BOR and PWRT
The on-chip regulator has a BOR circuit that resets the
device when the V
DD is too low (VDD < VBOR) for proper
device operation. The BOR circuit keeps the device in
Reset until VDD crosses the VBOR threshold and the
delay, T
BOR, has elapsed. The delay, TBOR, ensures
the voltage regulator output becomes stable.
The Brown-out Reset (BOR) status bit in the Reset
Control (RCON<1>) register is set to indicate the
Brown-out Reset.
The device will not run at full speed after a BOR as the
V
DD should rise to acceptable levels for full-speed
operation. The Power-up Timer (PWRT) provides power-
up time delay (TPWRT) to ensure that the system power
supplies have stabilized at the appropriate levels for
full-speed operation before the SYSRST is released.
Refer to Section 23.0 “Special Features” for further
details.
Figure 6-3 shows the typical brown-out scenarios. The
Reset delay (T
BOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point.
FIGURE 6-3: BROWN-OUT RESET SITUATIONS
VDD
SYSRST
VBOR
VDD
SYSRST
VBOR
VDD
SYSRST
VBOR
T BOR + T PWRT
VDD Dips Before PWRT Expires
T BOR + T PWRT
T BOR + T PWRT