Datasheet

 2011-2014 Microchip Technology Inc. DS70000652F-page 223
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
bit 1 SAMP: ADC1 Sample Enable bit
1 = ADC1 Sample-and-Hold amplifiers are sampling
0 = ADC1 Sample-and-Hold amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling; automatically set by hardware if ASAM = 1. If
SSRC<2:0> = 000, software can write ‘0’ to end sampling and start conversion. If SSRC<2:0> 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0 DONE: ADC1 Conversion Status bit
1 = ADC1 conversion cycle is completed
0 = ADC1 conversion has not started or is in progress
Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear the
DONE bit status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in
progress. Automatically cleared by hardware at start of a new conversion.
REGISTER 19-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)
Note 1: This feature is available in dsPIC33FJ(16/32)MC10X devices only.