Datasheet

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70000652F-page 168  2011-2014 Microchip Technology Inc.
FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
(1,3,4)
Set TxIF
Equal
Comparator
PRx
PRy
Reset
LSbMSb
Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the TxCON register.
2: The ADC event trigger is available only on Timer2/3.
3: Timer4/5 is available in dsPIC33FJ32(GP/MC)10X devices only.
4: Where ‘x’ or ‘y’ is present, x = 2 or 4; y = 3 or 5.
Data Bus<15:0>
TMRxHLD
Read TMRx/TMRy
Write TMRx/TMRy
16
16
16
Q
Q
D
CK
TGATE
0
1
TON
TCKPS<1:0>
2
T
CY
TCS
1x
01
TGATE
00
TxCK
ADC Event Trigger
(2)
Gate
Sync
Prescaler
1, 8, 64, 256
Sync
TMRx
TMRy
16
To CTMU Filter