Datasheet

2009-2014 Microchip Technology Inc. DS7000591F-page 65
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 4-9: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608
File
Name
SFR
Addr
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR MATHERR ADDRERR STKERR OSCFAIL
0000
INTCON2 0082 ALTIVT DISI INT4EP INT3EP INT2EP INT1EP INT0EP
0000
IFS0 0084 ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF
0000
IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF INT1IF CNIF AC1IF MI2C1IF SI2C1IF
0000
IFS2 0088 IC4IF IC3IF —SPI2IFSPI2EIF
0000
IFS3 008A QEI1IF PSEMIF INT4IF INT3IF MI2C2IF SI2C2IF
0000
IFS4 008C QEI2IF PSESMIF —U2EIFU1EIF
0000
IFS5 008E PWM2IF PWM1IF ADCP12IF —ADCP8IF
0000
IFS6 0090 ADCP1IF ADCP0IF AC4IF AC3IF AC2IF PWM8IF PWM7IF PWM6IF PWM5IF PWM4IF PWM3IF
0000
IFS7 0092 ADCP7IF ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF
0000
IEC0 0094 ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE
0000
IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE INT1IE CNIE MI2C1IE SI2C1IE
0000
IEC2 0098 —IC4IEIC3IE —SPI2IESPI2EIE
0000
IEC3 009A QEI1IE PSEMIE INT4IE INT3IE MI2C2IE SI2C2IE
0000
IEC4 009C QEI2IE PSESMIE —U2EIEU1EIE
0000
IEC5 009E PWM2IE PWM1IE ADCP12IE ADCP8IE
0000
IEC6 00A0 ADCP1IE ADCP0IE AC4IE AC3IE AC2IE PWM8IE PWM7IE PWM6IE PWM5IE PWM4IE PWM3IE
0000
IEC7 00A2 ADCP7IE ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE
0000
IPC0 00A4 T1IP2 T1IP1 T1IP0 OC1IP2 OC1IP1 OC1IP0 IC1IP2 IC1IP1 IC1IP0 INT0IP2 INT0IP1 INT0IP0
4444
IPC1 00A6 T2IP2 T2IP1 T2IP0 OC2IP2 OC2IP1 OC2IP0 IC2IP2 IC2IP1 IC2IP0
4440
IPC2 00A8 U1RXIP2 U1RXIP1 U1RXIP0 SPI1IP2 SPI1IP1 SPI1IP0 SPI1EIP2 SPI1EIP1 SPI1EIP0 —T3IP2T3IP1T3IP0
4444
IPC3 00AA ADIP2 ADIP1 ADIP0 U1TXIP2 U1TXIP1 U1TXIP0
0044
IPC4 00AC CNIP2 CNIP1 CNIP0 AC1IP2 AC1IP1 AC1IP0 MI2C1IP2 MI2C1IP1 MI2C1IP0 SI2C1IP2 SI2C1IP1 SI2C1IP0
4444
IPC5 00AE INT1IP2 INT1IP1 INT1IP0
0004
IPC6 00B0 T4IP2 T4IP1 T4IP0 OC4IP2 OC4IP1 OC4IP0 OC3IP2 OC3IP1 OC3IP0
4440
IPC7 00B2 U2TXIP2 U2TXIP1 U2TXIP0 U2RXIP2 U2RXIP1 U2RXIP0 INT2IP2 INT2IP1 INT2IP0 —T5IP2T5IP1T5IP0
4444
IPC8 00B4 SPI2IP2 SPI2IP1 SPI2IP0 SPI2EIP2 SPI2EIP1 SPI2EIP0
0044
IPC9 00B6 IC4IP2 IC4IP1 IC4IP0 IC3IP2 IC3IP1 IC3IP0
0440
IPC12 00BC MI2C2IP2 MI2C2IP1 MI2C2IP0 SI2C2IP2 SI2C2IP1 SI2C2IP0
0440
IPC13 00BE INT4IP2 INT4IP1 INT4IP0 INT3IP2 INT3IP1 INT3IP0
0440
IPC14 00C0 QEI1IP2 QEI1IP1 QEI1IP0 PSEMIP2 PSEMIP1 PSEMIP0
0440
IPC16 00C4 U2EIP2 U2EIP1 U2EIP0 U1EIP2 U1EIP1 U1EIP0
0440
IPC18 00C8 QEI2IP2 QEI2IP1 QEI2IP0 PSESMIP2 PSESMIP1 PSESMIP0
4040
IPC20 00CC ADCP8IP2 ADCP8IP1 ADCP8IP0
0040
Legend:
x
= unknown value on Reset, — = unimplemented, read as
0
’. Reset values are shown in hexadecimal.