Datasheet

2009-2014 Microchip Technology Inc. DS70000591F-page 377
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No.
Symbol Characteristic Min Typ
(1)
Max Units Conditions
V
IL Input Low Voltage
DI10 I/O Pins V
SS —0.2VDD V
DI15 MCLR
VSS —0.2VDD V
DI16 I/O Pins with OSC1 or SOSCI V
SS —0.2VDD V
DI18 I/O Pins with SDAx, SCLx VSS —0.3 VDD V SMBus disabled
DI19 I/O Pins with SDAx, SCLx VSS 0.8 V SMBus enabled
V
IH Input High Voltage
DI20
DI21
I/O Pins Non 5V Tolerant
(4)
I/O Pins 5V Tolerant
(4)
0.7 VDD
0.7 VDD
VDD
5.5
V
V
DI28
DI29
SDAx, SCLx
SDAx, SCLx
0.7 V
DD
2.1
5.5
5.5
V
V
SMBus disabled
SMBus enabled
ICNPU CNx Pull-up Current
DI30 250 AV
DD = 3.3V, VPIN = VSS
IIL Input Leakage Current
(2,3,4)
DI50 I/O Pins with:
4x Driver Pins: RA0-RA7, RA14,
RA15, RB0-RB15
(10)
, RC1-RC4,
RC12-RC14, RD0-RD2,
RD8-RD12, RD14, RD15, RE8,
RE9, RF0-RF8, RF12, RF13,
RG0-RG3, RG6-RG9, RG14, RG15
8x Driver Pins: RC15
16x Driver Pins: RA9, RA10,
RD3-RD7, RD13, RE0-RE7,
RG12, RG13
±2
±4
±8
A
A
A
V
SS VPIN VDD,
Pin at high-impedance
VSS VPIN VDD,
Pin at high-impedance
V
SS VPIN VDD,
Pin at high-impedance
DI55 MCLR
——±2AVSS VPIN VDD
DI56 OSC1 ±2 AVSS VPIN VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR
pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: See the Pin Diagrams section for the list of 5V tolerant I/O pins.
5: V
IL source < (VSS – 0.3). Characterized but not tested.
6: V
IH source > (VDD + 0.3) for non-5V tolerant pins only.
7: Digital 5V tolerant pins do not have an internal high side diode to V
DD, and therefore, cannot tolerate any
“positive” input injection current.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under I
ICL or IICH conditions are permitted,
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
10: RB11 has also been tested up to ±8 µA test limits.