Datasheet

 2009-2014 Microchip Technology Inc. DS70000591F-page 339
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 22-11: ADCPC5: ADC CONVERT PAIR CONTROL REGISTER 5
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN11 PEND11 SWTRG11
TRGSRC114 TRGSRC113 TRGSRC112 TRGSRC111 TRGSRC110
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN10 PEND10 SWTRG10
TRGSRC104 TRGSRC103 TRGSRC102 TRGSRC101 TRGSRC100
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 IRQEN11: Interrupt Request Enable 11 bit
1 = Enables IRQ generation when requested conversion of Channels AN23 and AN22 is completed
0 = IRQ is not generated
bit 14 PEND11: Pending Conversion Status 11 bit
1 = Conversion of Channels AN23 and AN22 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13 SWTRG11: Software Trigger 11 bit
1 = Starts conversion of AN23 and AN22 (if selected by the TRGSRCx<4:0> bits)
(1)
This bit is automatically cleared by hardware when the PEND11 bit is set.
0 = Conversion is not started
Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.