Datasheet

 2009-2014 Microchip Technology Inc. DS70000591F-page 333
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 22-9: ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN7 PEND7 SWTRG7
TRGSRC74 TRGSRC73 TRGSRC72 TRGSRC71 TRGSRC70
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN6 PEND6 SWTRG6
TRGSRC64 TRGSRC63 TRGSRC62 TRGSRC61 TRGSRC60
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 IRQEN7: Interrupt Request Enable 7 bit
1 = Enables IRQ generation when requested conversion of Channels AN15 and AN14 is completed
0 = IRQ is not generated
bit 14 PEND7: Pending Conversion Status 7 bit
1 = Conversion of Channels AN15 and AN14 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13 SWTRG7: Software Trigger 7 bit
1 = Starts conversion of AN15 and AN14 (if selected by the TRGSRCx<4:0> bits)
(1)
This bit is automatically cleared by hardware when the PEND7 bit is set.
0 = Conversion has not started
Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.