Datasheet

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70000591F-page 330  2009-2014 Microchip Technology Inc.
REGISTER 22-8: ADCPC2: ADC CONVERT PAIR CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN5 PEND5 SWTRG5
TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN4 PEND4 SWTRG4
TRGSRC44 TRGSRC43 TRGSRC42 TRGSRC41 TRGSRC40
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 IRQEN5: Interrupt Request Enable 5 bit
1 = Enables IRQ generation when requested conversion of Channels AN11 and AN10 is completed
0 = IRQ is not generated
bit 14 PEND5: Pending Conversion Status 5 bit
1 = Conversion of Channels AN11 and AN10 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13 SWTRG5: Software Trigger 5 bit
1 = Starts conversion of AN11 and AN10 (if selected by the TRGSRCx<4:0> bits)
(1)
This bit is automatically cleared by hardware when the PEND5 bit is set.
0 = Conversion has not started
Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.