Datasheet

 2009-2014 Microchip Technology Inc. DS70000591F-page 327

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRQEN3 PEND3 SWTRG3

TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRQEN2 PEND2 SWTRG2

TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 IRQEN3: Interrupt Request Enable 3 bit

1 = Enables IRQ generation when requested conversion of Channels AN7 and AN6 is completed

0 = IRQ is not generated

bit 14 PEND3: Pending Conversion Status 3 bit

1 = Conversion of Channels AN7 and AN6 is pending; set when selected trigger is asserted

0 = Conversion is complete

bit 13 SWTRG3: Software Trigger 3 bit

1 = Starts conversion of AN7 and AN6 (if selected by the TRGSRCx<4:0> bits)

(1)

This bit is automatically cleared by hardware when the PEND3 bit is set.

0 = Conversion has not started

Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other

conversions are in progress, the conversion is performed when the conversion resources are available.