Datasheet

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70000591F-page 320  2009-2014 Microchip Technology Inc.
bit 4 ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit
(1)
1 = The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger
pulse is detected
0 = The dedicated S&H starts sampling when the trigger event is detected and completes the sampling
process in two ADC clock cycles
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ADCS<2:0>: Analog-to-Digital Conversion Clock Divider Select bits
(1)
111 = FADC/8
110 = F
ADC/7
101 = F
ADC/6
100 = F
ADC/5
011 = F
ADC/4 (default)
010 = F
ADC/3
001 = F
ADC/2
000 = F
ADC/1
REGISTER 22-1: ADCON: ADC CONTROL REGISTER (CONTINUED)
Note 1: This control bit can only be changed while the ADC is disabled (ADON = 0).
2: This control bit is only active on devices that have one SAR.