Datasheet

 2009-2014 Microchip Technology Inc. DS70000591F-page 315
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 22-1: ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406
DEVICES WITH ONE SAR
Even Numbered Inputs with Dedicated
Shared Sample-and-Hold
Data
Format
SAR
Core
Sixteen
Registers
16-Bit
Sample-and-Hold (S&H) Circuits
Bus Interface
AN0
AN1
AN7
AN15
AN3
AN2
AN4
AN6
AN5
AN8
AN9
AN10
AN11
AN12
AN13
AN14