Datasheet

 2009-2014 Microchip Technology Inc. DS70000591F-page 291
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 21-4: CxFCTRL: ECANx FIFO CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
DMABS2 DMABS1 DMABS0 — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —FSA4
(1)
FSA3
(1)
FSA2
(1)
FSA1
(1)
FSA0
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 DMABS<2:0>: DMA Buffer Size bits
111 = Reserved
110 = 32 buffers in DMA RAM
101 = 24 buffers in DMA RAM
100 = 16 buffers in DMA RAM
011 = 12 buffers in DMA RAM
010 = 8 buffers in DMA RAM
001 = 6 buffers in DMA RAM
000 = 4 buffers in DMA RAM
bit 12-5 Unimplemented: Read as ‘0’
bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits
(1)
11111 = Reads Buffer RB31
11110 = Reads Buffer RB30
•
•
•
00001 = TX/RX Buffer TRB1
00000 = TX/RX Buffer TRB0
Note 1: FSA<4:0> bits are used to specify the start of the FIFO within the buffer area.