Datasheet

 2009-2014 Microchip Technology Inc. DS70000591F-page 281
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
bit 4 URXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
Note 1: Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on
enabling the UART module for receive or transmit operation. That section of the manual is available on the
Microchip web site: www.microchip.com.
2: This feature is only available for the 16x BRG mode (BRGH = 0).