Datasheet

 2009-2014 Microchip Technology Inc. DS70000591F-page 223
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 13-2: TyCON: TIMERy CONTROL REGISTER (y = 3, 5)
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON
(2)
—TSIDL
(1)
— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0
— TGATE
(2)
TCKPS1
(2)
TCKPS0
(2)
— —TCS
(2)
—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timery On bit
(2)
1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timery Stop in Idle Mode bit
(1)
1 = Discontinues timer operation when device enters Idle mode
0 = Continues timer operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer
y Gated Time Accumulation Enable bit
(2)
When TCS = 1:
This bit is ignored.
When TCS =
0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer
y Input Clock Prescale Select bits
(2)
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3-2 Unimplemented: Read as ‘0’
bit 1 TCS: Timer
y Clock Source Select bit
(2)
1 = External clock from TxCK pin
0 = Internal clock (F
OSC/2)
bit 0 Unimplemented: Read as ‘0’
Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
2: When the 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), these
bits have no effect.