Datasheet

 2009-2014 Microchip Technology Inc. DS70000591F-page 195

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

bit 3 CF: Clock Fail Detect bit (read/clear by application)

1 = FSCM has detected clock failure

0 = FSCM has not detected clock failure

bit 2-1 Unimplemented: Read as ‘0’

bit 0 OSWEN: Oscillator Switch Enable bit

1 = Requests oscillator switch to the selection specified by the NOSC<2:0> bits

0 = Oscillator switch is complete

(1)

(CONTINUED)

Note 1: Writes to this register require an unlock sequence. Refer to “Oscillator (Part IV)” (DS70307) in the

“dsPIC33/PIC24 Family Reference Manual” for details.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.

This applies to clock switches in either direction. In these instances, the application must switch to FRC

mode as a transition clock source between the two PLL modes.