Datasheet

 2009-2014 Microchip Technology Inc. DS70000591F-page 189
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
9.0 OSCILLATOR
CONFIGURATION
The oscillator system provides:
• External and Internal Oscillator Options as Clock
Sources
• An On-Chip Phase-Locked Loop (PLL) to Scale
the Internal Operating frequency to the Required
System Clock Frequency
• An Internal FRC Oscillator that can also be used
with the PLL, thereby allowing Full-Speed Operation
without any External Clock Generation Hardware
• Clock Switching Between Various Clock Sources
• Programmable Clock Postscaler for System
Power Savings
• A Fail-Safe Clock Monitor (FSCM) that Detects
Clock Failure and takes Fail-Safe Measures
• A Clock Control Register (OSCCON)
• Nonvolatile Configuration bits for Main Oscillator
Selection
• Auxiliary PLL for ADC and PWM
A simplified diagram of the oscillator system is shown
in Figure 9-1.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to “Oscillator (Part IV)”
(DS70307) in the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com). The information
in this data sheet supersedes the
information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.