Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70000318G-page 32  2008-2014 Microchip Technology Inc.
3.3 Special MCU Features
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
devices feature a 17-bit by 17-bit single-cycle multi-
plier that is shared by both the MCU ALU and DSP
engine. The multiplier can perform signed, unsigned
and mixed sign multiplication. Using a 17-bit by 17-bit
multiplier for 16-bit by 16-bit multiplication not only
allows you to perform mixed sign multiplication, it
also achieves accurate results for special operations,
such as (-1.0) x (1.0).
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 devices support 16/16 and 32/16 divide operations,
both fractional and integer. All divide instructions are iter-
ative operations. They must be executed within a REPEAT
loop, resulting in a total execution time of 19 instruction
cycles. The divide operation can be interrupted during any
of those 19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
FIGURE 3-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU CORE
BLOCK DIAGRAM
Instruction
Decode &
Control
PCH
Program Counter
24
23
Instruction Reg
PCU
ROM Latch
EA MUX
Interrupt
Controller
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Control Signals
to Various Blocks
Literal Data
16
16
16
To Peripheral Modules
Data Latch
Address
Latch
16
X RAM
Y RAM
Address Generator Units
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
16
23
23
16
8
PSV & Table
Data Access
Control Block
16
16
16
16
Program Memory
Data Latch
Address Latch
PCL
16 x 16
W Register Array
16-Bit ALU